74 FAST TTL Verilog Library

Verilog models of the 1980 catalog of Fairchild FAST (Advanced Schottky TTL) logic, with the data sheet transcription each one was written from.

The models carry data sheet propagation delays in specify blocks, so a design built out of them simulates with something close to the timing of the real parts. Each device below has its data sheet transcribed from the 1980 Fairchild FAST Data Book (supplemented by the 1981 and 1985 books), and most have a matching Verilog module and test bench. Ports are scalar and named after the data sheet pin names, because Icarus Verilog does not fully support multi-bit specify path connections.

74 devices, 58 with models.

Built with it

mgpr832 — an 8 x 32-bit register file, one write port and two read ports, 119 packages of 74F. The whole card is simulated with data sheet timing, out of a model generated from its KiCad netlist.

the mgpr832 register card PCB, a dense grid of 119 DIP packages

Devices

DeviceFunctionModel
74F00QUAD 2-INPUT NAND GATEf00.v
74F02QUAD 2-INPUT NOR GATEf02.v
74F04HEX INVERTERf04.v
74F08QUAD 2-INPUT AND GATEf08.v
74F10TRIPLE 3-INPUT NAND GATEf10.v
74F11TRIPLE 3-INPUT AND GATEf11.v
74F20DUAL 4-INPUT NAND GATEf20.v
74F32QUAD 2-INPUT OR GATEf32.v
74F644-2-3-2-INPUT AND-OR-INVERT GATEf64.v
74F74DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOPf74.v
74F86QUAD 2-INPUT EXCLUSIVE-OR GATEf86.v
74F109DUAL J/K POSITIVE EDGE-TRIGGERED FLIP-FLOPf109.v
74F112DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP—
74F1381-OF-8 DECODER/DEMULTIPLEXERf138.v
74F139DUAL 1-OF-4 DECODERf139.v
74F1518-INPUT MULTIPLEXERf151.v
74F153DUAL 4-INPUT MULTIPLEXERf153.v
74F157QUAD 2-INPUT MULTIPLEXERf157.v
74F158QUAD 2-INPUT MULTIPLEXERf158.v
74F160SYNCHRONOUS PRESETTABLE BCD DECADE COUNTERf160.v
74F161SYNCHRONOUS PRESETTABLE BINARY COUNTERf161.v
74F162SYNCHRONOUS PRESETTABLE BCD DECADE COUNTERf162.v
74F163SYNCHRONOUS PRESETTABLE BINARY COUNTERf163.v
74F1684-STAGE SYNCHRONOUS BIDIRECTIONAL COUNTER—
74F1694-STAGE SYNCHRONOUS BIDIRECTIONAL COUNTER—
74F175QUAD D FLIP-FLOPf175.v
74F1814-BIT ARITHMETIC LOGIC UNITf181.v
74F182CARRY LOOKAHEAD GENERATORf182.v
74F18964-BIT RANDOM ACCESS MEMORY (WITH 3-STATE OUTPUTS)f189.v
74F190UP/DOWN DECADE COUNTER (WITH PRESET AND RIPPLE CLOCK)f190.v
74F191UP/DOWN BINARY COUNTER (WITH PRESET AND RIPPLE CLOCK)f191.v
74F192UP/DOWN DECADE COUNTER (WITH SEPARATE UP/DOWN CLOCKS)f192.v
74F193UP/DOWN BINARY COUNTER (WITH SEPARATE UP/DOWN CLOCKS)f193.v
74F1944-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERf194.v
74F240OCTAL BUFFER/LINE DRIVER, INVERTING (WITH 3-STATE OUTPUTS)f240.v
74F241OCTAL BUFFER/LINE DRIVER (WITH 3-STATE OUTPUTS)f241.v
74F242QUAD BUS TRANSCEIVER, INVERTING (WITH 3-STATE OUTPUTS)f242.v
74F243QUAD BUS TRANSCEIVER (WITH 3-STATE OUTPUTS)f243.v
74F244OCTAL BUFFER/LINE DRIVER (WITH 3-STATE OUTPUTS)f244.v
74F245OCTAL BIDIRECTIONAL TRANSCEIVERf245.v
74F2518-INPUT MULTIPLEXER (WITH 3-STATE OUTPUTS)f251.v
74F253DUAL 4-INPUT MULTIPLEXER (WITH 3-STATE OUTPUTS)f253.v
74F257QUAD 2-INPUT MULTIPLEXER (WITH 3-STATE OUTPUTS)f257.v
74F258QUAD 2-INPUT MULTIPLEXER (WITH 3-STATE OUTPUTS)f258.v
74F2809-BIT PARITY GENERATOR/CHECKERf280.v
74F2834-BIT BINARY FULL ADDER (WITH FAST CARRY)f283.v
74F28964-BIT RANDOM ACCESS MEMORY (WITH OPEN-COLLECTOR OUTPUTS)f289.v
74F2998-INPUT UNIVERSAL SHIFT/STORAGE REGISTER—
74F3228-BIT SERIAL/PARALLEL REGISTER WITH SIGN EXTEND—
74F3238-BIT UNIVERSAL SHIFT/STORAGE REGISTER—
74F3504-BIT SHIFTER WITH 3-STATE OUTPUTS—
74F352DUAL 4-INPUT MULTIPLEXER (INVERTING)f352.v
74F353DUAL 4-INPUT MULTIPLEXER, INVERTINGf353.v
74F373OCTAL TRANSPARENT LATCH (WITH 3-STATE OUTPUTS)f373.v
74F374OCTAL D-TYPE FLIP-FLOP (WITH 3-STATE OUTPUTS)f374.v
74F379QUAD PARALLEL REGISTER (WITH ENABLE)f379.v
74F3814-BIT ARITHMETIC LOGIC UNIT—
74F3824-BIT ARITHMETIC LOGIC UNIT—
74F398QUAD 2-PORT REGISTER—
74F399QUAD 2-PORT REGISTER—
74F5006-BIT ANALOG-TO-DIGITAL FLASH CONVERTERf500.v
74F5218-BIT IDENTITY COMPARATORf521.v
74F5248-BIT REGISTERED COMPARATOR—
74F533OCTAL TRANSPARENT LATCH (3-STATE OUTPUTS)f533.v
74F534OCTAL D-TYPE FLIP-FLOP (3-STATE OUTPUTS)f534.v
74F5371-OF-10 DECODER (3-STATE OUTPUTS)f537.v
74F5381-OF-8 DECODER (3-STATE OUTPUTS)f538.v
74F539DUAL 1-OF-4 DECODER (3-STATE OUTPUTS)f539.v
74F545OCTAL BIDIRECTIONAL TRANSCEIVERf545.v
74F5578-BIT BY 8-BIT MULTIPLIER WITH LATCH—
74F5588-BIT BY 8-BIT MULTIPLIER—
74F5684-BIT BIDIRECTIONAL COUNTER WITH 3-STATE OUTPUTS—
74F5694-BIT BIDIRECTIONAL COUNTER WITH 3-STATE OUTPUTS—
74F588OCTAL BIDIRECTIONAL TRANSCEIVERf588.v

Building

Building and testing uses Icarus Verilog, driven by a Makefile:

make            build and run every testbench
make f00        build and run a single device's testbench
make list       list the known devices
make clean      remove build output

A testbench passes by printing TEST PASSED. The Makefile derives the device list from src/*.v, so adding a device needs no edit to it — just the src/<part>.v and tb/<part>_tb.v pair.

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