DESCRIPTION | CONNECTION DIAGRAM (14-pin DIP) | TRUTH TABLE | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | VERILOG MODEL
The 'F280 is a high speed parity generator/checker that accepts nine bits of input data and detects whether an even or an odd number of these inputs is HIGH. If an even number of inputs is HIGH, the Sum Even output is HIGH. If an odd number is HIGH, the Sum Even output is LOW. The Sum Odd output is the complement of the Sum Even output.
Pin Function Pin Function --- --------------------------- --- -------------------- 1 I6 Data input 6 14 Vcc 2 I7 Data input 7 13 I5 Data input 5 3 NC 12 I4 Data input 4 4 I8 Data input 8 11 I3 Data input 3 5 Sum-E Even Parity output 10 I2 Data input 2 6 Sum-O Odd Parity output 9 I1 Data input 1 7 GND 8 I0 Data input 0 Pin 3 is no-connect.
Number of inputs I0 - I8 that are HIGH Sum EVEN Sum ODD -------------------------------------- -------- ------- 0, 2, 4, 6, 8 H L 1, 3, 5, 7, 9 L H H = HIGH voltage level; L = LOW voltage level.
Pin Names Description U.L. HIGH/LOW --------- ------------------ ------------- I0 - I8 Data Inputs 0.5 / 0.375 Sigma-O Odd Parity Output 25 / 12.5 Sigma-E Even Parity Output 25 / 12.5
(Unless otherwise specified.) Symbol Parameter Min Typ Max Units Conditions ------ -------------------- --- --- --- ----- ---------- ICC Power Supply Current 25 mA Vcc = Max
Symbol Propagation Delay Path Min Typ Max Units ------ ---------------------- --- ---- --- ----- tPLH In to Sigma-E -- 12.5 -- ns tPHL In to Sigma-E -- 10.5 -- ns tPLH In to Sigma-O -- 12.5 -- ns tPHL In to Sigma-O -- 10.5 -- ns
Data sheet transcription as plain text
// ============================================================================ // f280.v — 54F/74F280 9-Bit Parity Generator/Checker // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F280.txt (1980 Fairchild FAST Data Book, // pages 4-85 ... 4-86) — PRELIMINARY data sheet // // Function (data sheet truth table): // even number (0,2,4,6,8) of inputs i0..i8 HIGH -> sum_even HIGH, sum_odd LOW // odd number (1,3,5,7,9) of inputs i0..i8 HIGH -> sum_even LOW, sum_odd HIGH // sum_odd is the complement of sum_even. // // Timing values from the data sheet AC Characteristics table, // 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF). // NOTE: the preliminary data sheet lists TYPICAL values only; the Min/Max // columns were left blank, so each specparam carries the typ value alone. // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f280 ( input wire i0, // data input 0 input wire i1, // data input 1 input wire i2, // data input 2 input wire i3, // data input 3 input wire i4, // data input 4 input wire i5, // data input 5 input wire i6, // data input 6 input wire i7, // data input 7 input wire i8, // data input 8 output wire sum_even, // Sum Even output (Sigma_E): HIGH for even parity output wire sum_odd // Sum Odd output (Sigma_O): HIGH for odd parity ); // Odd parity of the nine inputs; Sum Even is its complement. wire par = i0 ^ i1 ^ i2 ^ i3 ^ i4 ^ i5 ^ i6 ^ i7 ^ i8; assign sum_even = ~par; assign sum_odd = par; specify // Propagation delay I_n to Sum Even (data sheet: tPLH 12.5, // tPHL 10.5 ns — typ only, preliminary sheet, min/max blank) specparam tlh_i_se = 12.5; specparam thl_i_se = 10.5; // Propagation delay I_n to Sum Odd (data sheet: tPLH 12.5, // tPHL 10.5 ns — typ only, preliminary sheet, min/max blank) specparam tlh_i_so = 12.5; specparam thl_i_so = 10.5; (i0, i1, i2, i3, i4, i5, i6, i7, i8 => sum_even) = (tlh_i_se, thl_i_se); (i0, i1, i2, i3, i4, i5, i6, i7, i8 => sum_odd) = (tlh_i_so, thl_i_so); endspecify endmodule