DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (20-pin DIP) | MODE SELECT TABLE | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | AC OPERATING REQUIREMENTS
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Family: Fairchild FAST (Advanced Schottky TTL)
Source: 1985 Fairchild FAST Data Book, pages 4-209 ... 4-212. The 1980
data book carries the 'F323 in its Section 3 selection guide
only (page 3-19, description and logic symbol).
Status: Released data sheet
Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C
The 'F323 is an 8-bit universal shift/storage register with 3-state outputs. Its function is similar to the 'F299 with the exception of Synchronous Reset. Parallel load inputs and flip-flop outputs are multiplexed to minimize pin count. Separate serial inputs and outputs are provided for Q0 and Q7 to allow easy cascading. Four operation modes are possible: hold (store), shift left, shift right and parallel load. o Common Parallel I/O for Reduced Pin Count o Additional Serial Inputs and Outputs for Expansion o Four Operating Modes: Shift Left, Shift Right, Load and Store o 3-State Outputs for Bus-Oriented Applications
The 'F323 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous reset, shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1 as shown in the Mode Select Table. All flip-flop outputs are brought out through 3-state buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on /SR overrides the Select inputs and allows the flip-flops to be reset by the next rising edge of CP. All other state changes are also initiated by the LOW-to-HIGH CP transition. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either /OE1 or /OE2 disables the 3-state buffers and puts the I/O pins in the high impedance state. In this condition the shift, load, hold and reset operations can still occur. The 3-state buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation.
Pin Function Pin Function --- --------------------------- --- --------------------------- 1 S0 Mode Select 0 20 Vcc 2 /OE1 Output Enable 1 19 S1 Mode Select 1 3 /OE2 Output Enable 2 18 DS7 Serial Data, left shift 4 I/O6 Parallel I/O bit 6 17 Q7 Serial output 7 5 I/O4 Parallel I/O bit 4 16 I/O7 Parallel I/O bit 7 6 I/O2 Parallel I/O bit 2 15 I/O5 Parallel I/O bit 5 7 I/O0 Parallel I/O bit 0 14 I/O3 Parallel I/O bit 3 8 Q0 Serial output 0 13 I/O1 Parallel I/O bit 1 9 /SR Synchronous Reset 12 CP Clock Pulse 10 GND 11 DS0 Serial Data, right shift The even-numbered I/O pins are on the left side of the package and the odd-numbered ones on the right, so I/O0 - I/O7 are not in pin order. Both /OE1 and /OE2 must be LOW to enable the I/O pins.
Inputs ------------------ /SR S1 S0 CP Response --- -- -- --- --------------------------------------- L X X ^ Synchronous Reset; Q0-Q7 = LOW H H H ^ Parallel Load; I/On -> Qn H L H ^ Shift Right; DS0 -> Q0, Q0 -> Q1, etc. H H L ^ Shift Left; DS7 -> Q7, Q7 -> Q6, etc. H L L X Hold H = HIGH voltage level; L = LOW voltage level; X = immaterial. ^ = LOW-to-HIGH transition of CP.
Pin Names Description U.L. HIGH/LOW
------------ ----------------------------------------- -------------
CP Clock Pulse Input (Active Rising Edge) 0.5 / 0.375
DS0 Serial Data Input for Right Shift 0.5 / 0.375
DS7 Serial Data Input for Left Shift 0.5 / 0.375
S0, S1 Mode Select Inputs 0.5 / 0.75
/SR Synchronous Reset Input (Active LOW) 0.5 / 0.375
/OE1, /OE2 3-State Output Enable Inputs (Active LOW) 0.5 / 0.375
I/O0 - I/O7 Multiplexed Parallel Data Inputs 1.75 / 0.406
3-State Parallel Data Outputs 75 / 15
Q0, Q7 Serial Outputs 25 / 12.5
Symbol Parameter Min Typ Max Units Conditions
------ -------------------- --- --- --- ----- --------------------
ICC Power Supply Current 68 95 mA Vcc = Max, CP = HIGH
Outputs Disabled
TA = +25 C 74F
Vcc = +5.0V TA/Vcc = Com
Symbol Parameter CL Min Typ Max Min Max Units
------ ----------------------------- ----- --- ---- --- --- ---- -----
fmax Maximum Input Frequency -- 70 100 -- 70 -- MHz
tPLH Prop Delay CP to Q0 or Q7 50 pF 4.0 7.0 9.0 4.0 10.0 ns
tPHL Prop Delay CP to Q0 or Q7 50 pF 3.5 6.5 8.5 3.5 9.5 ns
tPLH Prop Delay CP to I/On 50 pF 4.0 7.0 9.0 4.0 10.0 ns
tPHL Prop Delay CP to I/On 50 pF 5.0 8.5 11.0 5.0 12.0 ns
tPZH Output Enable Time 50 pF 3.5 6.0 8.0 3.5 9.0 ns
tPZL Output Enable Time 50 pF 4.0 7.0 10.0 4.0 11.0 ns
tPHZ Output Disable Time 50 pF 2.5 4.5 6.0 2.5 7.0 ns
tPLZ Output Disable Time 50 pF 2.0 4.0 5.5 2.0 6.5 ns
TA = +25 C 74F
Vcc = +5.0V TA/Vcc = Com
Symbol Parameter Min Typ Max Min Max Units
------ -------------------------------------- --- --- --- --- --- -----
ts (H) Setup Time, HIGH -- S0 or S1 to CP 8.5 -- -- 8.5 -- ns
ts (L) Setup Time, LOW -- S0 or S1 to CP 8.5 -- -- 8.5 -- ns
th (H) Hold Time, HIGH -- S0 or S1 to CP 0 -- -- 0 -- ns
th (L) Hold Time, LOW -- S0 or S1 to CP 0 -- -- 0 -- ns
ts (H) Setup Time, HIGH -- I/On, DS0, DS7 to CP 5.0 -- -- 5.0 -- ns
ts (L) Setup Time, LOW -- I/On, DS0, DS7 to CP 5.0 -- -- 5.0 -- ns
th (H) Hold Time, HIGH -- I/On, DS0, DS7 to CP 2.0 -- -- 2.0 -- ns
th (L) Hold Time, LOW -- I/On, DS0, DS7 to CP 2.0 -- -- 2.0 -- ns
ts (H) Setup Time, HIGH -- /SR to CP 10.0 -- -- 10.0 -- ns
ts (L) Setup Time, LOW -- /SR to CP 10.0 -- -- 10.0 -- ns
th (H) Hold Time, HIGH -- /SR to CP 0 -- -- 0 -- ns
th (L) Hold Time, LOW -- /SR to CP 0 -- -- 0 -- ns
tw (H) CP Pulse Width, HIGH 7.0 -- -- 7.0 -- ns
tw (L) CP Pulse Width, LOW 7.0 -- -- 7.0 -- ns
Data sheet transcription as plain text
No model for this device yet — only the data sheet transcription above.