DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (16-pin DIP) | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | VERILOG MODEL
The 'F283 high speed 4-bit binary full adder with internal carry lookahead accepts two 4-bit binary words (A0 - A3, B0 - B3) and a Carry input (C0). It generates the binary Sum outputs (S0 - S3) and the Carry output (C4) from the most significant bit. The 'F283 will operate with either active HIGH or active LOW operands (positive or negative logic).
The 'F283 adds two 4-bit binary words (A plus B) plus the incoming
carry C0. The binary sum appears on the Sum (S0 - S3) and outgoing
carry (C4) outputs. The binary weight of the various inputs and outputs
is indicated by the subscript numbers, representing powers of two.
2^0 (A0 + B0 + C0) + 2^1 (A1 + B1) + 2^2 (A2 + B2) + 2^3 (A3 + B3)
= S0 + 2S1 + 4S2 + 8S3 + 16C4
Where (+) = plus
Interchanging inputs of equal weight does not affect the operation.
Thus C0, A0, B0 can be arbitrarily assigned to pins 5, 6 and 7. Due to
the symmetry of the binary add function, the 'F283 can be used either
with all inputs and outputs active HIGH (positive logic) or with all
inputs and outputs active LOW (negative logic). Note that if C0 is not
used it must be tied LOW for active HIGH logic or tied HIGH for active
LOW logic.
Example:
C0 A0 A1 A2 A3 B0 B1 B2 B3 S0 S1 S2 S3 C4
-- -- -- -- -- -- -- -- -- -- -- -- -- --
Logic Levels L L H L H H L L H H H L L H
Active HIGH 0 0 1 0 1 1 0 0 1 1 1 0 0 1
Active LOW 1 1 0 1 0 0 1 1 0 0 0 1 1 0
Active HIGH: 0 + 10 + 9 = 3 + 16 Active LOW: 1 + 5 + 6 = 12 + 0
Due to pin limitations, the intermediate carries of the 'F283 are not
brought out for use as inputs or outputs. However, other means can be
used to effectively insert a carry into, or bring a carry out from, an
intermediate stage. Figure a shows how to make a 3-bit adder. Tying the
operand inputs of the fourth adder (A3, B3) LOW makes S3 dependent only
on, and equal to, the carry from the third adder. Using somewhat the
same principle, Figure b shows a way of dividing the 'F283 into a 2-bit
and a 1-bit adder. The third stage adder (A2, B2, S2) is used merely as
a means of getting a carry (C10) signal into the fourth stage (via A2
and B2) and bringing out the carry from the second stage on S2. Note
that as long as A2 and B2 are the same, whether HIGH or LOW, they do
not influence S2. Similarly, when A2 and B2 are the same the carry into
the third stage does not influence the carry out of the third stage.
Figure c shows a method of implementing a 5-input encoder, where the
inputs are equally weighted. The outputs S0, S1 and S2 present a binary
number equal to the number of inputs I1 - I5 that are true. Figure d
shows one method of implementing a 5-input majority gate. When three or
more of the inputs I1 - I5 are true, the output M5 is true.
Pin Function Pin Function --- ---------------------- --- ---------------------- 1 S1 Sum output 1 16 Vcc 2 B1 B operand input 1 15 B2 B operand input 2 3 A1 A operand input 1 14 A2 A operand input 2 4 S0 Sum output 0 13 S2 Sum output 2 5 A0 A operand input 0 12 A3 A operand input 3 6 B0 B operand input 0 11 B3 B operand input 3 7 C0 Carry input 10 S3 Sum output 3 8 GND 9 C4 Carry output
Pin Names Description U.L. HIGH/LOW --------- ---------------- ------------- A0 - A3 A Operand Inputs 0.5 / 0.375 B0 - B3 B Operand Inputs 0.5 / 0.375 C0 Carry Input 0.5 / 0.375 S0 - S3 Sum Outputs 25 / 12.5 C4 Carry Output 25 / 12.5
(Unless otherwise specified.) Symbol Parameter Min Typ Max Units Conditions ------ -------------------- --- --- --- ----- ------------------------- ICC Power Supply Current 30 mA Vcc = Max, Inputs = 4.5 V
Symbol Propagation Delay Path Min Typ Max Units ------ ---------------------- --- --- --- ----- tPLH C0 to Sn -- 8.2 -- ns tPHL C0 to Sn -- 7.5 -- ns tPLH An or Bn to Sn -- 8.5 -- ns tPHL An or Bn to Sn -- 8.5 -- ns tPLH C0 to C4 -- 4.7 -- ns tPHL C0 to C4 -- 4.7 -- ns tPLH An or Bn to C4 -- 4.7 -- ns tPHL An or Bn to C4 -- 4.7 -- ns
Data sheet transcription as plain text
// ============================================================================ // f283.v — 54F/74F283 4-Bit Binary Full Adder (With Fast Carry) // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F283.txt (1980 Fairchild FAST Data Book, // pages 4-87 ... 4-90) — PRELIMINARY data sheet // // Function (data sheet functional description): // 2^0(a0 + b0 + c0) + 2^1(a1 + b1) + 2^2(a2 + b2) + 2^3(a3 + b3) // = s0 + 2*s1 + 4*s2 + 8*s3 + 16*c4 // i.e. {c4, s3, s2, s1, s0} = a + b + c0. The same binary add realizes the // data sheet's active-HIGH (positive logic) and active-LOW (negative logic) // interpretations. // // Timing values from the data sheet AC Characteristics table, // 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF). // NOTE: the preliminary data sheet lists TYPICAL values only; the Min/Max // columns were left blank, so each specparam carries the typ value alone. // The sheet gives one figure for "A_n or B_n to S_n" and one for "A_n or B_n // to C4"; they are applied here to every output functionally dependent on // the operand input (an operand bit also feeds the higher sum bits and C4 // through the internal carry lookahead). The carry path (C0 to C4, 4.7 ns) // is roughly half the carry-to-sum path — the point of the fast carry. // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f283 ( input wire a0, // A operand input 0 input wire a1, // A operand input 1 input wire a2, // A operand input 2 input wire a3, // A operand input 3 input wire b0, // B operand input 0 input wire b1, // B operand input 1 input wire b2, // B operand input 2 input wire b3, // B operand input 3 input wire c0, // carry input output wire s0, // sum output 0 output wire s1, // sum output 1 output wire s2, // sum output 2 output wire s3, // sum output 3 output wire c4 // carry output ); wire [4:0] total = {1'b0, a3, a2, a1, a0} + {1'b0, b3, b2, b1, b0} + c0; assign s0 = total[0]; assign s1 = total[1]; assign s2 = total[2]; assign s3 = total[3]; assign c4 = total[4]; specify // Propagation delay C0 to S_n (data sheet: tPLH 8.2, tPHL 7.5 ns — // typ only, preliminary sheet, min/max blank) specparam tlh_c_s = 8.2; specparam thl_c_s = 7.5; // Propagation delay A_n or B_n to S_n (data sheet: tPLH 8.5, // tPHL 8.5 ns — typ only, preliminary sheet, min/max blank) specparam tlh_ab_s = 8.5; specparam thl_ab_s = 8.5; // Propagation delay C0 to C4 (data sheet: tPLH 4.7, tPHL 4.7 ns — // typ only, preliminary sheet, min/max blank) specparam tlh_c_c4 = 4.7; specparam thl_c_c4 = 4.7; // Propagation delay A_n or B_n to C4 (data sheet: tPLH 4.7, // tPHL 4.7 ns — typ only, preliminary sheet, min/max blank) specparam tlh_ab_c4 = 4.7; specparam thl_ab_c4 = 4.7; // Carry input paths (c0 => s0) = (tlh_c_s, thl_c_s); (c0 => s1) = (tlh_c_s, thl_c_s); (c0 => s2) = (tlh_c_s, thl_c_s); (c0 => s3) = (tlh_c_s, thl_c_s); (c0 => c4) = (tlh_c_c4, thl_c_c4); // Operand input paths: each a_n/b_n feeds its own sum bit and, // via the lookahead carry, every higher sum bit and C4. (a0, b0 => s0) = (tlh_ab_s, thl_ab_s); (a0, b0, a1, b1 => s1) = (tlh_ab_s, thl_ab_s); (a0, b0, a1, b1, a2, b2 => s2) = (tlh_ab_s, thl_ab_s); (a0, b0, a1, b1, a2, b2, a3, b3 => s3) = (tlh_ab_s, thl_ab_s); (a0, b0, a1, b1, a2, b2, a3, b3 => c4) = (tlh_ab_c4, thl_ab_c4); endspecify endmodule