DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (16-pin DIP) | MODE SELECT TABLE | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | AC OPERATING REQUIREMENTS | VERILOG MODEL
The 'F194 is a high speed 4-bit bidirectional universal shift register. As a high speed multifunctional sequential building block, it is useful in a wide variety of applications. It may be used in serial-serial, shift left, shift right, serial-parallel, parallel-serial, and parallel-parallel data register transfers. The 'F194 is similar in operation to the 'S195 universal shift register, with added features of shift left without external connections and hold (do nothing) modes of operation. o TYPICAL SHIFT FREQUENCY OF 150 MHz o ASYNCHRONOUS MASTER RESET o HOLD (DO NOTHING) MODE o FULLY SYNCHRONOUS SERIAL OR PARALLEL DATA TRANSFERS
The 'F194 contains four edge-triggered D flip-flops and the necessary interstage logic to synchronously perform shift right, shift left, parallel load and hold operations. Signals applied to the Select (S0, S1) inputs determine the type of operation, as shown in the Mode Select Table. Signals on the Select, Parallel data (P0 - P3) and Serial data (DSR, DSL) inputs can change when the clock is in either state, provided only that the recommended setup and hold times, with respect to the clock rising edge, are observed. A LOW signal on Master Reset (/MR) overrides all other inputs and forces the outputs LOW.
The pin descriptions run long, so the two-up diagram is given as the two sides of the package in turn. Pins 1 - 8, left side of the package: Pin Function --- ------------------------------------------- 1 /MR Asynchronous Master Reset (active LOW) 2 DSR Serial Data Input (Shift Right) 3 P0 Parallel data input 0 4 P1 Parallel data input 1 5 P2 Parallel data input 2 6 P3 Parallel data input 3 7 DSL Serial Data Input (Shift Left) 8 GND Pins 16 - 9, right side of the package: Pin Function --- ------------------------------------------- 16 Vcc 15 Q0 Parallel output 0 14 Q1 Parallel output 1 13 Q2 Parallel output 2 12 Q3 Parallel output 3 11 CP Clock Pulse (active rising edge) 10 S1 Mode Control input 1 9 S0 Mode Control input 0
Operating Mode /MR S1 S0 DSR DSL Pn Q0 Q1 Q2 Q3
-------------- --- --- --- --- --- --- --- --- --- ---
Reset L X X X X X L L L L
Hold H l l X X X q0 q1 q2 q3
Shift Left H h l X l X q1 q2 q3 L
Shift Left H h l X h X q1 q2 q3 H
Shift Right H l h l X X L q0 q1 q2
Shift Right H l h h X X H q0 q1 q2
Parallel Load H h h X X pn p0 p1 p2 p3
l = LOW voltage level one setup time prior to the LOW-to-HIGH clock
transition.
h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock
transition.
pn (qn) = Lower case letters indicate the state of the referenced input
(or output) one setup time prior to the LOW-to-HIGH clock transition.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Pin Names Description U.L. HIGH/LOW --------- -------------------------------------------- ------------- S0, S1 Mode Control Inputs 0.5 / 0.375 P0 - P3 Parallel Data Inputs 0.5 / 0.375 DSR Serial Data Input (Shift Right) 0.5 / 0.375 DSL Serial Data Input (Shift Left) 0.5 / 0.375 CP Clock Pulse Input (Active Rising Edge) 0.5 / 0.375 /MR Asynchronous Master Reset Input (Active LOW) 0.5 / 0.375 Q0 - Q3 Parallel Outputs 25 / 12.5
Conditions for all rows: Vcc = Max; Sn, /MR, DSR, DSL = 4.5 V;
Pn = Gnd; CP = ^ (rising edge).
Symbol Parameter Min Typ Max Units
------ -------------------- --- --- --- -----
ICC Power Supply Current 33 46 mA
Symbol Parameter Min Typ Max Units ------ --------------------------- --- --- --- ----- fmax Maximum Shift Frequency 105 150 -- MHz tPLH Propagation Delay CP to Qn 2.0 4.0 7.0 ns tPHL Propagation Delay CP to Qn 2.0 4.5 9.0 ns tPHL Propagation Delay /MR to Qn 5.0 10 13 ns
Symbol Parameter Min Typ Max Units ------ ---------------------------------------- --- --- --- ----- ts (H) Setup Time, HIGH -- Pn, DSR or DSL to CP 4.0 -- -- ns ts (L) Setup Time, LOW -- Pn, DSR or DSL to CP 4.0 -- -- ns th (H) Hold Time, HIGH -- Pn, DSR or DSL to CP 0 -- -- ns th (L) Hold Time, LOW -- Pn, DSR or DSL to CP 0 -- -- ns ts (H) Setup Time, HIGH -- Sn to CP 8.0 -- -- ns ts (L) Setup Time, LOW -- Sn to CP 8.0 -- -- ns th (H) Hold Time, HIGH -- Sn to CP 0 -- -- ns th (L) Hold Time, LOW -- Sn to CP 0 -- -- ns tw (H) CP Pulse Width HIGH 5.0 -- -- ns tw (L) /MR Pulse Width LOW 5.0 -- -- ns trec Recovery Time -- /MR to CP 7.0 -- -- ns
Data sheet transcription as plain text
// ============================================================================ // f194.v — 54F/74F194 4-Bit Bidirectional Universal Shift Register // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F194.txt (1980 Fairchild FAST Data Book, // pages 4-65 ... 4-67) // // Mode select table (data sheet), synchronous on the rising edge of CP: // S1 S0 | Operation // ------+---------------------------------------------------------- // L L | Hold (do nothing) // L H | Shift Right: Q0 <- DSR, Q1 <- Q0, Q2 <- Q1, Q3 <- Q2 // H L | Shift Left: Q0 <- Q1, Q1 <- Q2, Q2 <- Q3, Q3 <- DSL // H H | Parallel Load: Qn <- Pn // // A LOW on MR_n (asynchronous Master Reset) overrides all other inputs and // forces all four outputs LOW. // // Timing values from the data sheet AC Characteristics table, // 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), min:typ:max ns. // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f194 ( input wire mr_n, // asynchronous master reset (active LOW) input wire cp, // clock pulse (active rising edge) input wire s0, // mode control input 0 input wire s1, // mode control input 1 input wire dsr, // serial data input (shift right) input wire dsl, // serial data input (shift left) input wire p0, p1, p2, p3, // parallel data inputs output reg q0, q1, q2, q3 // parallel outputs ); always @(posedge cp or negedge mr_n) begin if (!mr_n) begin q0 <= 1'b0; q1 <= 1'b0; q2 <= 1'b0; q3 <= 1'b0; end else begin case ({s1, s0}) 2'b00: ; // hold 2'b01: begin // shift right (toward Q3) q0 <= dsr; q1 <= q0; q2 <= q1; q3 <= q2; end 2'b10: begin // shift left (toward Q0) q0 <= q1; q1 <= q2; q2 <= q3; q3 <= dsl; end 2'b11: begin // parallel load q0 <= p0; q1 <= p1; q2 <= p2; q3 <= p3; end endcase end end specify // Maximum shift frequency (data sheet: fmax 105 min / 150 typ MHz, // max blank on the sheet), Fig. 2-17 / 2-21. Not a path delay; // recorded here for completeness, applied to no path. specparam fmax_min_mhz = 105; specparam fmax_typ_mhz = 150; // Propagation delay CP to Q_n (data sheet: tPLH 2.0/4.0/7.0, // tPHL 2.0/4.5/9.0 ns), Fig. 2-17, 2-21. specparam tlh_cp_q = 2.0:4.0:7.0; specparam thl_cp_q = 2.0:4.5:9.0; // Propagation delay MR_n to Q_n (data sheet: tPHL 5.0/10/13 ns), // Fig. 2-17, 2-24. Only tPHL exists: MR_n can only drive Q LOW. // Single-delay form (applies to every transition; only 1->0 occurs). specparam thl_mr_q = 5.0:10:13; (cp => q0) = (tlh_cp_q, thl_cp_q); (cp => q1) = (tlh_cp_q, thl_cp_q); (cp => q2) = (tlh_cp_q, thl_cp_q); (cp => q3) = (tlh_cp_q, thl_cp_q); (mr_n => q0) = (thl_mr_q); (mr_n => q1) = (thl_mr_q); (mr_n => q2) = (thl_mr_q); (mr_n => q3) = (thl_mr_q); // AC operating requirements (data sheet, +25 C 5.0 V minima): // ts(H/L) P_n/DSR/DSL to CP 4.0, th(H/L) 0; ts(H/L) S_n to CP 8.0, // th(H/L) 0; tw(H) CP 5.0; tw(L) MR_n 5.0; trec MR_n to CP 7.0 ns. // Icarus Verilog does not support timing checks; kept (guarded) // for simulators that do. `ifndef __ICARUS__ specparam ts_d_h = 4.0; // ts(H) P_n, DSR or DSL to CP specparam ts_d_l = 4.0; // ts(L) P_n, DSR or DSL to CP specparam th_d_h = 0; // th(H) P_n, DSR or DSL to CP specparam th_d_l = 0; // th(L) P_n, DSR or DSL to CP specparam ts_s_h = 8.0; // ts(H) S_n to CP specparam ts_s_l = 8.0; // ts(L) S_n to CP specparam th_s_h = 0; // th(H) S_n to CP specparam th_s_l = 0; // th(L) S_n to CP specparam tw_cp_h = 5.0; // CP pulse width HIGH specparam tw_mr_l = 5.0; // MR_n pulse width LOW specparam trec = 7.0; // recovery time, MR_n to CP $setup(p0, posedge cp, ts_d_h); $setup(p1, posedge cp, ts_d_h); $setup(p2, posedge cp, ts_d_h); $setup(p3, posedge cp, ts_d_h); $setup(dsr, posedge cp, ts_d_h); $setup(dsl, posedge cp, ts_d_h); $hold(posedge cp, p0, th_d_h); $hold(posedge cp, p1, th_d_h); $hold(posedge cp, p2, th_d_h); $hold(posedge cp, p3, th_d_h); $hold(posedge cp, dsr, th_d_h); $hold(posedge cp, dsl, th_d_h); $setup(s0, posedge cp, ts_s_h); $setup(s1, posedge cp, ts_s_h); $hold(posedge cp, s0, th_s_h); $hold(posedge cp, s1, th_s_h); $width(posedge cp, tw_cp_h); $width(negedge mr_n, tw_mr_l); $recovery(posedge mr_n, posedge cp, trec); `endif endspecify endmodule