DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (16-pin DIP) | TRUTH TABLE (each side) | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | VERILOG MODEL
The 'F153 is a high speed dual 4-input multiplexer with common select inputs and individual enable inputs for each section. It can select two lines of data from four sources. The two buffered outputs present data in the true (non-inverted) form. In addition to multiplexer operation, the 'F153 can generate any two functions of three variables.
The 'F153 can select two bits of data from up to four sources under the
control of the common Select inputs (S0, S1). The two 4-input
multiplexer circuits have individual active LOW Enables (/Ea, /Eb) which
can be used to strobe the outputs independently. When the Enables are
HIGH, the corresponding outputs (Za, Zb) are forced LOW.
The 'F153 is the logic implementation of a 2-pole, 4-position switch,
where the position of the switch is determined by the logic levels
supplied to the two Select inputs.
Za = /Ea * ( I0a*/S1*/S0 + I1a*/S1*S0 + I2a*S1*/S0 + I3a*S1*S0 )
Zb = /Eb * ( I0b*/S1*/S0 + I1b*/S1*S0 + I2b*S1*/S0 + I3b*S1*S0 )
The 'F153 can be used to move data from a group of registers to a common
output bus; the particular register from which the data came would be
determined by the state of the Select inputs. A less obvious
application is as a FUNCTION GENERATOR -- the 'F153 can generate two
functions of three variables, which is useful for implementing highly
irregular random logic.
Pin Function Pin Function --- ------------------------------- --- ------------------------------- 1 /Ea Side A Enable (active LOW) 16 Vcc 2 S1 Common Select 1 15 /Eb Side B Enable (active LOW) 3 I3a Side A data input 3 14 S0 Common Select 0 4 I2a Side A data input 2 13 I3b Side B data input 3 5 I1a Side A data input 1 12 I2b Side B data input 2 6 I0a Side A data input 0 11 I1b Side B data input 1 7 Za Side A output 10 I0b Side B data input 0 8 GND 9 Zb Side B output
S0 S1 /E I0 I1 I2 I3 Z -- -- -- -- -- -- -- - X X H X X X X L L L L L X X X L L L L H X X X H H L L X L X X L H L L X H X X H L H L X X L X L L H L X X H X H H H L X X X L L H H L X X X H H H = HIGH Voltage Level; L = LOW Voltage Level; X = Immaterial. The table applies to each side. For the A side, read /E as /Ea, I0 - I3 as I0a - I3a and Z as Za; for the B side, read /E as /Eb, I0 - I3 as I0b - I3b and Z as Zb. S0 and S1 are common to both sides.
Pin Names Description U.L. HIGH/LOW ----------- -------------------------------- ------------- I0a - I3a Side A Data Inputs 0.5 / 0.375 I0b - I3b Side B Data Inputs 0.5 / 0.375 S0, S1 Common Select Inputs 0.5 / 0.375 /Ea Side A Enable Input (Active LOW) 0.5 / 0.375 /Eb Side B Enable Input (Active LOW) 0.5 / 0.375 Za Side A Output 25 / 12.5 Zb Side B Output 25 / 12.5
Symbol Description Min Typ Max Units Conditions ------ -------------------- --- --- --- ----- -------------------- ICC Power Supply Current 12 20 mA Vcc = Max, VIN = Gnd
Symbol Parameter Min Typ Max Units ------ --------------------------- --- --- --- ----- tPLH Propagation Delay Sn to Zn 3.0 9.5 13 ns tPHL Propagation Delay Sn to Zn 3.0 8.0 10 ns tPLH Propagation Delay /En to Zn 3.0 8.0 12 ns tPHL Propagation Delay /En to Zn 3.0 7.5 12 ns tPLH Propagation Delay In to Zn 2.0 5.0 8.0 ns tPHL Propagation Delay In to Zn 2.0 4.5 6.5 ns
Data sheet transcription as plain text
// ============================================================================ // f153.v — 54F/74F153 Dual 4-Input Multiplexer // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F153.txt (1980 Fairchild FAST Data Book, // pages 4-19 ... 4-21) // // Two 4-input multiplexers with COMMON Select inputs (S0, S1) and // individual active-LOW Enables (ea_n, eb_n). The outputs present data in // the true (non-inverted) form. When an Enable is HIGH, the corresponding // output is forced LOW regardless of all other inputs. // // za = ~ea_n & (selected I_na) // zb = ~eb_n & (selected I_nb) // // Timing values from the data sheet AC Characteristics table, // 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), min:typ:max ns. // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f153 ( input wire i0a, i1a, i2a, i3a, // side A data inputs 0-3 input wire i0b, i1b, i2b, i3b, // side B data inputs 0-3 input wire s0, s1, // common select inputs input wire ea_n, // side A enable (active LOW) input wire eb_n, // side B enable (active LOW) output wire za, // side A output output wire zb // side B output ); // Selected data inputs (internal nodes) wire da = s1 ? (s0 ? i3a : i2a) : (s0 ? i1a : i0a); wire db = s1 ? (s0 ? i3b : i2b) : (s0 ? i1b : i0b); assign za = ~ea_n & da; assign zb = ~eb_n & db; specify // Propagation delay S_n to Z_n (data sheet: 3.0/9.5/13, // 3.0/8.0/10 ns) specparam tlh_s_z = 3.0:9.5:13; specparam thl_s_z = 3.0:8.0:10; // Propagation delay E_n to Z_n (data sheet: 3.0/8.0/12, // 3.0/7.5/12 ns) specparam tlh_e_z = 3.0:8.0:12; specparam thl_e_z = 3.0:7.5:12; // Propagation delay I_n to Z_n (data sheet: 2.0/5.0/8.0, // 2.0/4.5/6.5 ns) specparam tlh_i_z = 2.0:5.0:8.0; specparam thl_i_z = 2.0:4.5:6.5; (s0, s1 => za) = (tlh_s_z, thl_s_z); (s0, s1 => zb) = (tlh_s_z, thl_s_z); (ea_n => za) = (tlh_e_z, thl_e_z); (eb_n => zb) = (tlh_e_z, thl_e_z); (i0a, i1a, i2a, i3a => za) = (tlh_i_z, thl_i_z); (i0b, i1b, i2b, i3b => zb) = (tlh_i_z, thl_i_z); endspecify endmodule