DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (16-pin DIP) | TRUTH TABLE (each section) | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | VERILOG MODEL
The 'F157 is a high speed quad 2-input multiplexer. Four bits of data from two sources can be selected using the common Select and Enable inputs. The four buffered outputs present the selected data in the true (non-inverted) form. The 'F157 can also be used to generate any four of the 16 different functions to two variables. The inverting counterpart is the 'F158.
The 'F157 selects four bits of data from two sources under the control
of a common Select input (S). The Enable input (/E) is ACTIVE LOW.
When /E is HIGH, all of the outputs (Z) are forced LOW regardless of all
other inputs.
The 'F157 is the logic implementation of a 4-pole, 2-position switch
where the position of the switch is determined by the logic levels
supplied to the Select input.
Za = /E * ( I1a*S + I0a*/S ) Zb = /E * ( I1b*S + I0b*/S )
Zc = /E * ( I1c*S + I0c*/S ) Zd = /E * ( I1d*S + I0d*/S )
A common use of the 'F157 is the moving of data from two groups of
registers to four common output busses; the particular register from
which the data comes is determined by the state of the Select input. A
less obvious use is as a function generator -- the 'F157 can generate
any four of the 16 different functions of two variables with one
variable common, which is useful for implementing highly irregular
logic.
Pin Function Pin Function --- -------------------- --- ------------------------------ 1 S Select input 16 Vcc 2 I0a Source 0, bit a 15 /E Enable input (active LOW) 3 I1a Source 1, bit a 14 I0c Source 0, bit c 4 Za Output a 13 I1c Source 1, bit c 5 I0b Source 0, bit b 12 Zc Output c 6 I1b Source 1, bit b 11 I0d Source 0, bit d 7 Zb Output b 10 I1d Source 1, bit d 8 GND 9 Zd Output d
/E S I0 I1 Z
-- -- -- -- -
H X X X L
L H X L L
L H X H H
L L L X L
L L H X H
H = HIGH voltage level; L = LOW voltage level; X = immaterial.
Summary: S = LOW selects the I0 (source 0) inputs; S = HIGH selects
the I1 (source 1) inputs.
The table applies to each of the four sections a, b, c, d: read I0 as
I0a ... I0d, I1 as I1a ... I1d and Z as Za ... Zd. S and /E are common
to all four sections.
Pin Names Description U.L. HIGH/LOW ----------- ------------------------- ------------- I0a - I0d Source 0 Data Inputs 0.5 / 0.375 I1a - I1d Source 1 Data Inputs 0.5 / 0.375 /E Enable Input (Active LOW) 0.5 / 0.375 S Select Input 0.5 / 0.375 Za - Zd Outputs 25 / 12.5
Test conditions: Vcc = Max, All Inputs = 4.5 V Symbol Parameter Min Typ Max Units ------ -------------------- --- --- --- ----- ICC Power Supply Current 14 23 mA
Symbol Parameter Min Typ Max Units ------ -------------------------- --- --- --- ----- tPLH Propagation Delay S to Zn 4.0 8.5 13 ns tPHL Propagation Delay S to Zn 3.0 6.0 9.0 ns tPLH Propagation Delay /E to Zn 2.0 6.5 8.0 ns tPHL Propagation Delay /E to Zn 2.0 4.5 7.0 ns tPLH Propagation Delay In to Zn 2.0 4.5 6.0 ns tPHL Propagation Delay In to Zn 2.0 3.5 4.5 ns
Data sheet transcription as plain text
// ============================================================================ // f157.v — 54F/74F157 Quad 2-Input Multiplexer // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F157.txt (1980 Fairchild FAST Data Book, // pages 4-22 ... 4-24) // // Four 2-input multiplexers with a common Select input (S) and a common // active-LOW Enable (e_n). S LOW selects the I0 (source 0) inputs, S HIGH // selects the I1 (source 1) inputs. The outputs present data in the true // (non-inverted) form. When e_n is HIGH, all outputs are forced LOW // regardless of all other inputs. // // zn = ~e_n & (s ? i1n : i0n) // // Timing values from the data sheet AC Characteristics table, // 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), min:typ:max ns. // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f157 ( input wire s, // select input (common) input wire e_n, // enable input (active LOW) input wire i0a, i1a, // source 0/1 data inputs, bit a output wire za, // output a input wire i0b, i1b, // source 0/1 data inputs, bit b output wire zb, // output b input wire i0c, i1c, // source 0/1 data inputs, bit c output wire zc, // output c input wire i0d, i1d, // source 0/1 data inputs, bit d output wire zd // output d ); assign za = ~e_n & (s ? i1a : i0a); assign zb = ~e_n & (s ? i1b : i0b); assign zc = ~e_n & (s ? i1c : i0c); assign zd = ~e_n & (s ? i1d : i0d); specify // Propagation delay S to Z_n (data sheet: 4.0/8.5/13, // 3.0/6.0/9.0 ns) specparam tlh_s_z = 4.0:8.5:13; specparam thl_s_z = 3.0:6.0:9.0; // Propagation delay E_n to Z_n (data sheet: 2.0/6.5/8.0, // 2.0/4.5/7.0 ns) specparam tlh_e_z = 2.0:6.5:8.0; specparam thl_e_z = 2.0:4.5:7.0; // Propagation delay I_n to Z_n (data sheet: 2.0/4.5/6.0, // 2.0/3.5/4.5 ns) specparam tlh_i_z = 2.0:4.5:6.0; specparam thl_i_z = 2.0:3.5:4.5; (s => za) = (tlh_s_z, thl_s_z); (s => zb) = (tlh_s_z, thl_s_z); (s => zc) = (tlh_s_z, thl_s_z); (s => zd) = (tlh_s_z, thl_s_z); (e_n => za) = (tlh_e_z, thl_e_z); (e_n => zb) = (tlh_e_z, thl_e_z); (e_n => zc) = (tlh_e_z, thl_e_z); (e_n => zd) = (tlh_e_z, thl_e_z); (i0a, i1a => za) = (tlh_i_z, thl_i_z); (i0b, i1b => zb) = (tlh_i_z, thl_i_z); (i0c, i1c => zc) = (tlh_i_z, thl_i_z); (i0d, i1d => zd) = (tlh_i_z, thl_i_z); endspecify endmodule