DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (20-pin DIP) | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | AC OPERATING REQUIREMENTS | VERILOG MODEL
The 'F373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (/OE) is LOW. When /OE is HIGH the bus output is in the high impedance state. o EIGHT LATCHES IN A SINGLE PACKAGE o 3-STATE OUTPUTS FOR BUS INTERFACING
The 'F373 contains eight D-type latches with 3-state output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-state buffers are controlled by the Output Enable (/OE) input. When /OE is LOW, the buffers are in the bi-state mode. When /OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches.
Pin Function Pin Function --- ------------------------------- --- ------------------------------- 1 /OE Output Enable (active LOW) 20 Vcc 2 O0 Latch output 0 19 O7 Latch output 7 3 D0 Data input 0 18 D7 Data input 7 4 D1 Data input 1 17 D6 Data input 6 5 O1 Latch output 1 16 O6 Latch output 6 6 O2 Latch output 2 15 O5 Latch output 5 7 D2 Data input 2 14 D5 Data input 5 8 D3 Data input 3 13 D4 Data input 4 9 O3 Latch output 3 12 O4 Latch output 4 10 GND 11 LE Latch Enable (active HIGH)
Pin Names Description U.L. HIGH/LOW --------- -------------------------------- ------------- D0 - D7 Data Inputs 0.5 / 0.375 LE Latch Enable Input (Active HIGH) 0.5 / 0.375 /OE Output Enable Input (Active LOW) 0.5 / 0.375 O0 - O7 3-State Latch Outputs 25 / 12.5
Conditions for all rows: Vcc = Max, /OE = 4.5 V; Dn, LE = Gnd. Symbol Parameter Min Typ Max Units ------ -------------------------------------- --- --- --- ----- ICC Power Supply Current (All Outputs OFF) 35 55 mA
Symbol Parameter Min Typ Max Units ------ -------------------------- --- --- --- ----- tPLH Propagation Delay Dn to On 2.0 4.3 6.5 ns tPHL Propagation Delay Dn to On 1.0 2.7 4.5 ns tPLH Propagation Delay LE to On 4.0 9.2 13 ns tPHL Propagation Delay LE to On 2.0 4.2 6.5 ns tPZH Output Enable Time 3.0 6.8 11 ns tPZL Output Enable Time 3.0 6.0 10 ns tPHZ Output Disable Time (1) 3.0 5.7 9.0 ns tPLZ Output Disable Time (1) 3.0 6.2 9.0 ns (1) Disable times measured with CL = 5.0 pF.
Symbol Parameter Min Typ Max Units ------ ---------------------------- --- --- --- ----- ts (H) Setup Time, HIGH -- Dn to LE 2.0 -- -- ns ts (L) Setup Time, LOW -- Dn to LE 2.0 -- -- ns th (H) Hold Time, HIGH -- Dn to LE 3.0 -- -- ns th (L) Hold Time, LOW -- Dn to LE 3.0 -- -- ns tw (H) LE Pulse Width HIGH 6.0 -- -- ns
Data sheet transcription as plain text
// ============================================================================ // f373.v — 54F/74F373 Octal Transparent Latch (With 3-State Outputs) // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F373.txt (1980 Fairchild FAST Data Book, // pages 4-100 ... 4-102) // // Eight D-type latches with 3-state outputs. While Latch Enable (LE) is // HIGH the latches are transparent: O_n follows D_n. When LE is LOW the // latches hold the data present a setup time before the HIGH-to-LOW LE // transition. Output Enable (OE_n) LOW drives the outputs; OE_n HIGH forces // the high-impedance state without disturbing the latches. // // Timing values from the data sheet AC Characteristics table, // 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), min:typ:max ns. // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f373 ( input wire oe_n, // output enable (active LOW) input wire le, // latch enable (active HIGH) input wire d0, d1, d2, d3, // data inputs 0-3 input wire d4, d5, d6, d7, // data inputs 4-7 output wire o0, o1, o2, o3, // 3-state latch outputs 0-3 output wire o4, o5, o6, o7 // 3-state latch outputs 4-7 ); // Transparent latch bank: Q follows D while LE is HIGH, holds while LOW. reg [7:0] q_int; always @(*) begin if (le) q_int <= {d7, d6, d5, d4, d3, d2, d1, d0}; end // 3-state output buffers (OE_n HIGH -> high impedance) assign o0 = oe_n ? 1'bz : q_int[0]; assign o1 = oe_n ? 1'bz : q_int[1]; assign o2 = oe_n ? 1'bz : q_int[2]; assign o3 = oe_n ? 1'bz : q_int[3]; assign o4 = oe_n ? 1'bz : q_int[4]; assign o5 = oe_n ? 1'bz : q_int[5]; assign o6 = oe_n ? 1'bz : q_int[6]; assign o7 = oe_n ? 1'bz : q_int[7]; specify // Propagation delay D_n to O_n (data sheet: tPLH 2.0/4.3/6.5, // tPHL 1.0/2.7/4.5 ns) specparam tlh_d_o = 2.0:4.3:6.5; specparam thl_d_o = 1.0:2.7:4.5; // Propagation delay LE to O_n (data sheet: tPLH 4.0/9.2/13, // tPHL 2.0/4.2/6.5 ns) specparam tlh_le_o = 4.0:9.2:13; specparam thl_le_o = 2.0:4.2:6.5; // Output enable/disable time OE_n to O_n (data sheet: // tPZH 3.0/6.8/11, tPZL 3.0/6.0/10, tPHZ 3.0/5.7/9.0, // tPLZ 3.0/6.2/9.0 ns; disable times measured with C_L = 5 pF) specparam tzh_oe_o = 3.0:6.8:11; specparam tzl_oe_o = 3.0:6.0:10; specparam thz_oe_o = 3.0:5.7:9.0; specparam tlz_oe_o = 3.0:6.2:9.0; // 6-delay form, IEEE order (0->1, 1->0, 0->Z, Z->1, 1->Z, Z->0): // D_n causes only 0->1/1->0 transitions, OE_n only Z transitions. (oe_n, d0 => o0) = (tlh_d_o, thl_d_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oe_n, d1 => o1) = (tlh_d_o, thl_d_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oe_n, d2 => o2) = (tlh_d_o, thl_d_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oe_n, d3 => o3) = (tlh_d_o, thl_d_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oe_n, d4 => o4) = (tlh_d_o, thl_d_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oe_n, d5 => o5) = (tlh_d_o, thl_d_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oe_n, d6 => o6) = (tlh_d_o, thl_d_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oe_n, d7 => o7) = (tlh_d_o, thl_d_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (le => o0) = (tlh_le_o, thl_le_o); (le => o1) = (tlh_le_o, thl_le_o); (le => o2) = (tlh_le_o, thl_le_o); (le => o3) = (tlh_le_o, thl_le_o); (le => o4) = (tlh_le_o, thl_le_o); (le => o5) = (tlh_le_o, thl_le_o); (le => o6) = (tlh_le_o, thl_le_o); (le => o7) = (tlh_le_o, thl_le_o); // AC operating requirements (data sheet, +25 C 5.0 V minima): // ts(H) 2.0, ts(L) 2.0, th(H) 3.0, th(L) 3.0, tw(H) LE 6.0 ns. // Setup/hold are relative to the HIGH-to-LOW LE edge that closes // the latch. Icarus Verilog does not support timing checks; kept // (guarded) for simulators that do. `ifndef __ICARUS__ specparam ts_h = 2.0; specparam ts_l = 2.0; specparam th_h = 3.0; specparam th_l = 3.0; specparam tw_le_h = 6.0; $setup(d0, negedge le, ts_h); $setup(d1, negedge le, ts_h); $setup(d2, negedge le, ts_h); $setup(d3, negedge le, ts_h); $setup(d4, negedge le, ts_h); $setup(d5, negedge le, ts_h); $setup(d6, negedge le, ts_h); $setup(d7, negedge le, ts_h); $hold(negedge le, d0, th_h); $hold(negedge le, d1, th_h); $hold(negedge le, d2, th_h); $hold(negedge le, d3, th_h); $hold(negedge le, d4, th_h); $hold(negedge le, d5, th_h); $hold(negedge le, d6, th_h); $hold(negedge le, d7, th_h); $width(posedge le, tw_le_h); `endif endspecify endmodule