DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (16-pin DIP) | MODE SELECT TABLE | /RC TRUTH TABLE | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | AC OPERATING REQUIREMENTS | VERILOG MODEL
The 'F191 is a reversible modulo-16 binary counter featuring synchronous counting and asynchronous presetting. The preset feature allows the 'F191 to be used in programmable dividers. The Count Enable input, the Terminal Count output and the Ripple Clock output make possible a variety of methods of implementing multistage counters. In the counting modes, state changes are initiated by the rising edge of the clock. o High speed -- 130 MHz typical count frequency o Synchronous counting o Asynchronous parallel load o Cascadable
The 'F191 is a synchronous up/down 4-bit binary counter. It contains four edge-triggered flip-flops, with internal gating and steering logic to provide individual preset, count-up and count-down operations. Each circuit has an asynchronous parallel load capability permitting the counter to be preset to any desired number. When the Parallel Load (/PL) input is LOW, information present on the Parallel Data inputs (P0 - P3) is loaded into the counter and appears on the Q outputs. This operation overrides the counting functions, as indicated in the Mode Select Table. A HIGH signal on the /CE input inhibits counting. When /CE is LOW, internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input. The direction of counting is determined by the /U/D input signal, as indicated in the Mode Select Table. /CE and /U/D can be changed with the clock in either state, provided only that the recommended setup and hold times are observed. Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC) output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches maximum (15 for the 'F191) in the count-up mode. The TC output will then remain HIGH until a state change occurs, whether by counting or presetting or until /U/D is changed. The TC output should not be used as a clock signal because it is subject to decoding spikes. The TC signal is also used internally to enable the Ripple Clock (/RC) output. The /RC output is normally HIGH. When /CE is LOW and TC is HIGH, the /RC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multistage counters, as indicated in Figures a and b. In Figure a, each /RC output is used as the clock input for the next higher stage. This configuration is particularly advantageous when the clock source has a limited drive capability, since it drives only the first stage. To prevent counting in all stages it is only necessary to inhibit the first stage, since a HIGH signal on /CE inhibits the /RC output pulse, as indicated in the /RC Truth Table. A disadvantage of this configuration, in some applications, is the timing skew between state changes in the first and last stages. This represents the cumulative delay of the clock as it ripples through the preceding stages. A method of causing state changes to occur simultaneously in all stages is shown in Figure b. All clock inputs are driven in parallel and the /RC outputs propagate the carry/borrow signals in ripple fashion. In this configuration the LOW state duration of the clock must be long enough to allow the negative-going edge of the carry/borrow signal to ripple through to the last stage before the clock goes HIGH. There is no such restriction on the HIGH state duration of the clock, since the /RC output of any package goes HIGH shortly after its CP input goes HIGH. The configuration shown in Figure c avoids ripple delays and their associated restrictions. The /CE input for a given stage is formed by combining the TC signals from all the preceding stages. Note that in order to inhibit counting an enable signal must be included in each carry gate. The simple inhibit scheme of Figures a and b doesn't apply, because the TC output of a given stage is not affected by its own /CE.
Pin Function Pin Function --- --------------------------- --- -------------------------------- 1 P1 Parallel data input 1 16 Vcc 2 Q1 Flip-flop output 1 15 P0 Parallel data input 0 3 Q0 Flip-flop output 0 14 CP Clock Pulse 4 /CE Count Enable 13 /RC Ripple Clock output 5 /U/D Up/Down Count Control 12 TC Terminal Count output 6 Q2 Flip-flop output 2 11 /PL Parallel Load input 7 Q3 Flip-flop output 3 10 P2 Parallel data input 2 8 GND 9 P3 Parallel data input 3
/PL /CE /U/D CP Mode --- --- ---- --- --------------------- H L L ^ Count Up H L H ^ Count Down L X X X Preset (Asynchronous) H H X X No Change (Hold) H = HIGH voltage level; L = LOW voltage level; X = immaterial; ^ = LOW-to-HIGH transition.
/CE TC(1) CP /RC --- ----- ------- ------- L H (pulse) (pulse) H X X H X L X H (1) TC is generated internally.
Pin Names Description U.L. HIGH/LOW --------- --------------------------------------------- ------------- /CE Count Enable Input (Active LOW) 0.5 / 1.125 CP Clock Pulse Input (Active Rising Edge) 0.5 / 0.375 P0 - P3 Parallel Data Inputs 0.5 / 0.375 /PL Asynchronous Parallel Load Input (Active LOW) 0.5 / 0.375 /U/D Up/Down Count Control Input 0.5 / 0.375 Q0 - Q3 Flip-flop Outputs 25 / 12.5 /RC Ripple Clock Output (Active LOW) 25 / 12.5 TC Terminal Count Output (Active HIGH) 25 / 12.5
Symbol Parameter Min Typ Max Units Conditions ------ -------------------- --- --- --- ----- ---------- ICC Power Supply Current 38 55 mA Vcc = Max
Symbol Parameter Min Typ Max Units ------ --------------------------- --- --- --- ----- fmax Maximum Count Frequency 90 130 -- MHz tPLH Propagation Dly CP to Qn 2.0 4.5 8.0 ns tPHL Propagation Dly CP to Qn 2.0 5.5 9.0 ns tPLH Propagation Dly CP to TC 3.0 6.5 10 ns tPHL Propagation Dly CP to TC 4.0 8.5 12 ns tPLH Propagation Dly CP to /RC 2.0 4.5 7.0 ns tPHL Propagation Dly CP to /RC 2.0 4.0 7.0 ns tPLH Propagation Dly /CE to /RC 2.0 3.6 6.0 ns tPHL Propagation Dly /CE to /RC 2.0 3.5 6.0 ns tPLH Propagation Dly /U/D to /RC 6.0 10 16 ns tPHL Propagation Dly /U/D to /RC 4.0 8.0 12 ns tPLH Propagation Dly /U/D to TC 2.0 5.0 9.0 ns tPHL Propagation Dly /U/D to TC 2.0 5.5 9.0 ns tPLH Propagation Dly Pn to Qn 2.0 3.6 6.0 ns tPHL Propagation Dly Pn to Qn 3.0 6.3 10 ns tPLH Propagation Dly /PL to Qn 2.0 5.7 9.0 ns tPHL Propagation Dly /PL to Qn 3.0 6.2 10 ns
Symbol Parameter Min Typ Max Units ------ ----------------------------- --- --- --- ----- ts (H) Setup Time, HIGH -- Pn to /PL 5.0 -- -- ns ts (L) Setup Time, LOW -- Pn to /PL 5.0 -- -- ns th (H) Hold Time, HIGH -- Pn to /PL 3.0 -- -- ns th (L) Hold Time, LOW -- Pn to /PL 3.0 -- -- ns ts (L) Setup Time LOW -- /CE to CP 10 -- -- ns th (L) Hold Time LOW -- /CE to CP 0 -- -- ns tw (L) /PL Pulse Width LOW 5.0 -- -- ns tw (L) CP Pulse Width LOW 5.5 -- -- ns trec Recovery Time -- /PL to CP 6.0 -- -- ns
Data sheet transcription as plain text
// ============================================================================ // f191.v — 54F/74F191 Up/Down Binary Counter with Preset and Ripple Clock // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F191.txt (1980 Fairchild FAST Data Book, // pages 4-52 ... 4-56) // // Modes of operation, in order of precedence (data sheet Mode Select table): // 1. /PL LOW : asynchronous parallel load — Pn // appears on Qn immediately, // overriding all other inputs // 2. /PL HIGH, /CE LOW, /U/D LOW, CP ^ : count up // 3. /PL HIGH, /CE LOW, /U/D HIGH, CP ^: count down // 4. /PL HIGH, /CE HIGH : hold (no change) // // Count sequence is modulo-16 binary. UP: 0->1->...->15->0. DOWN: 0->15->...->1->0. // No illegal states. // // TC is normally LOW. Goes HIGH when count = 15 in count-up mode or // count = 0 in count-down mode. Remains HIGH until a state change (count // or preset) or a /U/D change. // // /RC is normally HIGH. When /CE = LOW and TC = HIGH, /RC follows CP: // /RC = CP (same polarity). Otherwise /RC = HIGH. // // Timing values from the data sheet AC Characteristics table, // 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), min:typ:max ns. // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f191 ( input wire cp, // clock pulse (active rising edge) input wire pl_n, // parallel load (active LOW, asynchronous) input wire ce_n, // count enable (active LOW) input wire ud_n, // up/down count control (LOW = count up) input wire p0, // parallel data input 0 input wire p1, // parallel data input 1 input wire p2, // parallel data input 2 input wire p3, // parallel data input 3 output wire q0, // flip-flop output 0 output wire q1, // flip-flop output 1 output wire q2, // flip-flop output 2 output wire q3, // flip-flop output 3 output wire tc, // terminal count (active HIGH) output wire rc_n // ripple clock (active LOW) ); // /PL idles HIGH, hence the previous-level register's initial value. A // CP edge arriving while /PL is LOW is consumed by the load branch, which // has priority, and leaves nothing pending; a CP edge after the load // counts normally, since only a genuine rising edge fires the block. reg [3:0] state; reg pl_d = 1'b1; always @(posedge cp or posedge pl_n or negedge pl_n) begin if (!pl_n || !pl_d) state <= {p3, p2, p1, p0}; else if (!ce_n) state <= ud_n ? state - 4'd1 : state + 4'd1; pl_d <= pl_n; end // /PL passes P straight to the outputs, overriding the state register, // which is what makes the load transparent to P while /PL is LOW. The // `!pl_d` term above recaptures P into the state register when /PL is // released. wire [3:0] cnt = !pl_n ? {p3, p2, p1, p0} : state; assign q0 = cnt[0]; assign q1 = cnt[1]; assign q2 = cnt[2]; assign q3 = cnt[3]; wire tc_int; assign tc_int = (!ud_n && cnt == 4'd15) || (ud_n && cnt == 4'd0); assign tc = tc_int; assign rc_n = (!ce_n && tc_int) ? cp : 1'b1; specify // CP to Qn: tPLH 2.0:4.5:8.0, tPHL 2.0:5.5:9.0 specparam tlh_cp_q = 2.0:4.5:8.0; specparam thl_cp_q = 2.0:5.5:9.0; // CP to TC: tPLH 3.0:6.5:10, tPHL 4.0:8.5:12 specparam tlh_cp_tc = 3.0:6.5:10; specparam thl_cp_tc = 4.0:8.5:12; // CP to /RC: tPLH 2.0:4.5:7.0, tPHL 2.0:4.0:7.0 specparam tlh_cp_rc = 2.0:4.5:7.0; specparam thl_cp_rc = 2.0:4.0:7.0; // /CE to /RC: tPLH 2.0:3.6:6.0, tPHL 2.0:3.5:6.0 specparam tlh_ce_rc = 2.0:3.6:6.0; specparam thl_ce_rc = 2.0:3.5:6.0; // /U/D to /RC: tPLH 6.0:10:16, tPHL 4.0:8.0:12 specparam tlh_ud_rc = 6.0:10:16; specparam thl_ud_rc = 4.0:8.0:12; // /U/D to TC: tPLH 2.0:5.0:9.0, tPHL 2.0:5.5:9.0 specparam tlh_ud_tc = 2.0:5.0:9.0; specparam thl_ud_tc = 2.0:5.5:9.0; // Pn to Qn: tPLH 2.0:3.6:6.0, tPHL 3.0:6.3:10 specparam tlh_p_q = 2.0:3.6:6.0; specparam thl_p_q = 3.0:6.3:10; // /PL to Qn: tPLH 2.0:5.7:9.0, tPHL 3.0:6.2:10 specparam tlh_pl_q = 2.0:5.7:9.0; specparam thl_pl_q = 3.0:6.2:10; (cp => q0) = (tlh_cp_q, thl_cp_q); (cp => q1) = (tlh_cp_q, thl_cp_q); (cp => q2) = (tlh_cp_q, thl_cp_q); (cp => q3) = (tlh_cp_q, thl_cp_q); (cp => tc) = (tlh_cp_tc, thl_cp_tc); (cp => rc_n) = (tlh_cp_rc, thl_cp_rc); (ce_n => rc_n) = (tlh_ce_rc, thl_ce_rc); (ud_n => rc_n) = (tlh_ud_rc, thl_ud_rc); (ud_n => tc) = (tlh_ud_tc, thl_ud_tc); (p0 => q0) = (tlh_p_q, thl_p_q); (p1 => q1) = (tlh_p_q, thl_p_q); (p2 => q2) = (tlh_p_q, thl_p_q); (p3 => q3) = (tlh_p_q, thl_p_q); (pl_n => q0) = (tlh_pl_q, thl_pl_q); (pl_n => q1) = (tlh_pl_q, thl_pl_q); (pl_n => q2) = (tlh_pl_q, thl_pl_q); (pl_n => q3) = (tlh_pl_q, thl_pl_q); // AC operating requirements (data sheet, +25 C 5.0 V minima) // Icarus Verilog does not support timing checks; kept (guarded) // for simulators that do. `ifndef __ICARUS__ specparam ts_p = 5.0; specparam th_p = 3.0; specparam ts_ce = 10.0; specparam th_ce = 0; specparam tw_pl_l = 5.0; specparam tw_cp_l = 5.5; specparam trec_pl = 6.0; $setup(p0, posedge pl_n, ts_p); $setup(p1, posedge pl_n, ts_p); $setup(p2, posedge pl_n, ts_p); $setup(p3, posedge pl_n, ts_p); $hold(posedge pl_n, p0, th_p); $hold(posedge pl_n, p1, th_p); $hold(posedge pl_n, p2, th_p); $hold(posedge pl_n, p3, th_p); $setup(ce_n, posedge cp, ts_ce); $hold(posedge cp, ce_n, th_ce); $width(negedge pl_n, tw_pl_l); $width(negedge cp, tw_cp_l); $recovery(posedge pl_n, posedge cp, trec_pl); `endif endspecify endmodule