DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (16-pin DIP) | TRUTH TABLE (each side) | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | VERILOG MODEL
The 'F352 is a very high speed dual 4-input multiplexer with Common Select inputs and individual Enable inputs for each section. It can select two bits of data from four sources. The two buffered outputs present data in the inverted (complementary) form. The 'F352 is the functional equivalent of the 'F153 except with inverted outputs. o INVERTED VERSION OF THE 'F153 o SEPARATE ENABLES FOR EACH MULTIPLEXER o INPUT CLAMP DIODE LIMITS HIGH SPEED TERMINATION EFFECTS
The 'F352 is a dual 4-input multiplexer. It selects two bits of data
from up to four sources under the control of the common Select inputs
(S0, S1). The two 4-input
multiplexer circuits have individual active LOW Enables (/Ea, /Eb)
which can be used to strobe the outputs independently. When the Enables
(/Ea, /Eb) are HIGH, the corresponding outputs (/Za, /Zb) are forced
HIGH.
/Za = NOT[ /Ea * ( I0a*/S1*/S0 + I1a*/S1*S0 + I2a*S1*/S0 + I3a*S1*S0 ) ]
/Zb = NOT[ /Eb * ( I0b*/S1*/S0 + I1b*/S1*S0 + I2b*S1*/S0 + I3b*S1*S0 ) ]
The 'F352 can be used to move data from a group of registers to a
common output bus; the particular register from which the data came
would be determined by the state of the Select inputs. A less obvious
application is as a function generator -- the 'F352 can generate two
functions of three variables, useful for implementing highly irregular
random logic.
Pin Function Pin Function --- ------------------------------- --- ------------------------------- 1 /Ea Side A Enable (active LOW) 16 Vcc 2 S1 Common Select 1 15 /Eb Side B Enable (active LOW) 3 I3a Side A data input 3 14 S0 Common Select 0 4 I2a Side A data input 2 13 I3b Side B data input 3 5 I1a Side A data input 1 12 I2b Side B data input 2 6 I0a Side A data input 0 11 I1b Side B data input 1 7 /Za Side A inverted output 10 I0b Side B data input 0 8 GND 9 /Zb Side B inverted output
S0 S1 /E I0 I1 I2 I3 /Z -- -- -- -- -- -- -- -- X X H X X X X H L L L L X X X H L L L H X X X L H L L X L X X H H L L X H X X L L H L X X L X H L H L X X H X L H H L X X X L H H H L X X X H L H = HIGH voltage level; L = LOW voltage level; X = immaterial.
Pin Names Description U.L. HIGH/LOW --------- -------------------------------- ------------- I0a - I3a Side A Data Inputs 0.5 / 0.375 I0b - I3b Side B Data Inputs 0.5 / 0.375 S0, S1 Common Select Inputs 0.5 / 0.375 /Ea Side A Enable Input (Active LOW) 0.5 / 0.375 /Eb Side B Enable Input (Active LOW) 0.5 / 0.375 /Za, /Zb Multiplexer Outputs (Inverted) 25 / 12.5
Symbol Parameter Min Typ Max Units Conditions ------ -------------------- --- --- --- ----- -------------------- Icc Power Supply Current 8.0 mA Vcc = Max; VIN = Gnd
Symbol Parameter Min Typ Max Units ------ ---------------------------- --- --- --- ----- tPLH Propagation Delay Sn to /Zn -- 6.3 -- ns tPHL Propagation Delay Sn to /Zn -- 6.2 -- ns tPLH Propagation Delay /En to /Zn -- 4.6 -- ns tPHL Propagation Delay /En to /Zn -- 4.5 -- ns tPLH Propagation Delay In to /Zn -- 2.9 -- ns tPHL Propagation Delay In to /Zn -- 2.8 -- ns
Data sheet transcription as plain text
// ============================================================================ // f352.v — 54F/74F352 Dual 4-Input Multiplexer (Inverting) // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F352.txt (1980 Fairchild FAST Data Book, // pages 4-94 ... 4-96) — PRELIMINARY data sheet // // Two 4-input multiplexers with COMMON Select inputs (S0, S1) and // individual active-LOW Enables (ea_n, eb_n); the functional equivalent of // the 'F153 except the outputs are INVERTED. When an Enable is HIGH, the // corresponding output is forced HIGH regardless of all other inputs. // // za_n = ea_n | ~(selected I_na) // zb_n = eb_n | ~(selected I_nb) // // Timing values from the data sheet AC Characteristics table, // 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF). The sheet is // preliminary: only TYPICAL values are given (min/max columns blank), so // every specparam carries the typ value only. // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f352 ( input wire i0a, i1a, i2a, i3a, // side A data inputs 0-3 input wire i0b, i1b, i2b, i3b, // side B data inputs 0-3 input wire s0, s1, // common select inputs input wire ea_n, // side A enable (active LOW) input wire eb_n, // side B enable (active LOW) output wire za_n, // side A inverted output output wire zb_n // side B inverted output ); // Selected data inputs (internal nodes) wire da = s1 ? (s0 ? i3a : i2a) : (s0 ? i1a : i0a); wire db = s1 ? (s0 ? i3b : i2b) : (s0 ? i1b : i0b); assign za_n = ea_n | ~da; assign zb_n = eb_n | ~db; specify // All values TYP only (preliminary data sheet; min/max columns // left blank), 54F/74F +25 C 5.0 V C_L = 15 pF. // Propagation delay S_n to Z_n (data sheet: typ 6.3 / 6.2 ns) specparam tlh_s_z = 6.3; specparam thl_s_z = 6.2; // Propagation delay E_n to Z_n (data sheet: typ 4.6 / 4.5 ns) specparam tlh_e_z = 4.6; specparam thl_e_z = 4.5; // Propagation delay I_n to Z_n (data sheet: typ 2.9 / 2.8 ns) specparam tlh_i_z = 2.9; specparam thl_i_z = 2.8; (s0, s1 => za_n) = (tlh_s_z, thl_s_z); (s0, s1 => zb_n) = (tlh_s_z, thl_s_z); (ea_n => za_n) = (tlh_e_z, thl_e_z); (eb_n => zb_n) = (tlh_e_z, thl_e_z); (i0a, i1a, i2a, i3a => za_n) = (tlh_i_z, thl_i_z); (i0b, i1b, i2b, i3b => zb_n) = (tlh_i_z, thl_i_z); endspecify endmodule