DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (16-pin DIP) | TRUTH TABLE | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) | AC CHARACTERISTICS | VERILOG MODEL
The 'F182 is a high speed carry lookahead generator. It is generally
used with the 'F181, 'F381 or 2901A 4-bit arithmetic logic unit to
provide high speed lookahead over word lengths of more than four bits.
o PROVIDES LOOKAHEAD CARRIES ACROSS A GROUP OF FOUR ALU'S
o MULTI-LEVEL LOOKAHEAD FOR HIGH SPEED ARTITHMETIC OPERATION OVER
LONG WORD LENGTHS
The 'F182 carry lookahead generator accepts up to four pairs of active
LOW Carry Propagate (/P0 - /P3) and Carry Generate (/G0 - /G3) signals
and an active HIGH Carry input (Cn) and provides anticipated active
HIGH carries (Cn+x, Cn+y, Cn+z) across four groups of binary adders.
The 'F182 also has active LOW Carry Propagate (/P) and Carry Generate
(/G) outputs which may be used for further levels of lookahead. The
logic equations provided at the outputs are:
Cn+x = G0 + P0*Cn
Cn+y = G1 + P1*G0 + P1*P0*Cn
Cn+z = G2 + P2*G1 + P2*P1*G0 + P2*P1*P0*Cn
/G = /(G3 + P3*G2 + P3*P2*G1 + P3*P2*P1*G0)
/P = /(P3*P2*P1*P0)
Also, the 'F182 can be used with binary ALUs in an active LOW or
active HIGH input operand mode. The connections to and from the ALU to
the carry lookahead generator are identical in both cases. Carries are
rippled between lookahead blocks. There are several possible
arrangements for the carry interconnects, but all achieve about the
same speed. A 28-bit ALU is formed by dropping the last 'F181 or 'F381.
Pin Function Pin Function --- ----------------------------- --- --------------------------- 1 /G1 Carry Generate input 1 16 Vcc 2 /P1 Carry Propagate input 1 15 /P2 Carry Propagate input 2 3 /G0 Carry Generate input 0 14 /G2 Carry Generate input 2 4 /P0 Carry Propagate input 0 13 Cn Carry input 5 /G3 Carry Generate input 3 12 Cn+x Carry output x 6 /P3 Carry Propagate input 3 11 Cn+y Carry output y 7 /P Carry Propagate output 10 /G Carry Generate output 8 GND 9 Cn+z Carry output z
H = HIGH voltage level; L = LOW voltage level; X = immaterial; blank = not relevant to that output. Cn+x ~~~~ Cn /G0 /P0 Cn+x -- --- --- ---- X H H L L H X L X L X H H X L H Cn+y ~~~~ Cn /G0 /P0 /G1 /P1 Cn+y -- --- --- --- --- ---- X X X H H L X H H H X L L H X H X L X X X L X H X L X X L H H X L X L H Cn+z ~~~~ Cn /G0 /P0 /G1 /P1 /G2 /P2 Cn+z -- --- --- --- --- --- --- ---- X X X X X H H L X X X H H H X L X H H H X H X L L H X H X H X L X X X X X L X H X X X L X X L H X L X X L X L H H X L X L X L H /G ~~ /G0 /G1 /P1 /G2 /P2 /G3 /P3 /G --- --- --- --- --- --- --- --- X X X X X H H H X X X H H H X H X H H H X H X H H H X H X H X H X X X X X L X L X X X L X X L L X L X X L X L L L X L X L X L L /P ~~ /P0 /P1 /P2 /P3 /P --- --- --- --- --- H X X X H X H X X H X X H X H X X X H H L L L L L
Pin Names Description U.L. HIGH/LOW ------------- ----------------------------------- ------------- Cn Carry Input 0.5 / 0.375 /G0, /G2 Carry Generate Inputs (Active LOW) 0.5 / 2.625 /G1 Carry Generate Input (Active LOW) 0.5 / 3.0 /G3 Carry Generate Input (Active LOW) 0.5 / 1.5 /P0, /P1 Carry Propagate Inputs (Active LOW) 0.5 / 1.5 /P2 Carry Propagate Input (Active LOW) 0.5 / 1.125 /P3 Carry Propagate Input (Active LOW) 0.5 / 1.75 Cn+x - Cn+z Carry Outputs 25 / 12.5 /G Carry Generate Output (Active LOW) 25 / 12.5 /P Carry Propagate Output (Active LOW) 25 / 12.5
Symbol Parameter Min Typ Max Units Cond. ------ --------------------------------------- --- --- --- ----- ----- ICCH Power Supply Current (All Outputs HIGH) 11 mA (1) ICCL Power Supply Current (All Outputs LOW) 19 mA (2) (1) Vcc = Max; /P3, /G3 = 4.5 V; all other inputs = Gnd (2) Vcc = Max; /G0, /G1, /G2 = 4.5 V; all other inputs = Gnd
Symbol Propagation Delay Path Min Typ Max Units ------ ----------------------------------- --- --- --- ----- tPLH Cn to Cn+x, Cn+y, Cn+z -- 4.6 -- ns tPHL Cn to Cn+x, Cn+y, Cn+z -- 4.5 -- ns tPLH /P0, /P1 or /P2 to Cn+x, Cn+y, Cn+z -- 2.9 -- ns tPHL /P0, /P1 or /P2 to Cn+x, Cn+y, Cn+z -- 2.8 -- ns tPLH /G0, /G1 or /G2 to Cn+x, Cn+y, Cn+z -- 2.9 -- ns tPHL /G0, /G1 or /G2 to Cn+x, Cn+y, Cn+z -- 2.8 -- ns tPLH /P1, /P2 or /P3 to /G -- 4.5 -- ns tPHL /P1, /P2 or /P3 to /G -- 4.3 -- ns tPLH /Gn to /G -- 4.5 -- ns tPHL /Gn to /G -- 4.3 -- ns tPLH /Pn to /P -- 5.0 -- ns tPHL /Pn to /P -- 4.8 -- ns
Data sheet transcription as plain text
// ============================================================================ // f182.v — 54F/74F182 Carry Lookahead Generator // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F182.txt (1980 Fairchild FAST Data Book, // pages 4-41 ... 4-44) // // Accepts four pairs of active-LOW Carry Propagate (/P0-/P3) and Carry // Generate (/G0-/G3) signals plus an active-HIGH Carry input (Cn), and // provides three active-HIGH carries (Cn+x, Cn+y, Cn+z) together with // active-LOW Carry Propagate (/P) and Carry Generate (/G) outputs. // // Logic equations (from data sheet, in terms of internal positive logic // Pn = ~p_n[x], Gn = ~g_n[x]): // Cn+x = G0 + P0 * Cn // Cn+y = G1 + P1 * G0 + P1 * P0 * Cn // Cn+z = G2 + P2 * G1 + P2 * P1 * G0 + P2 * P1 * P0 * Cn // /G = ~(G3 + P3 * G2 + P3 * P2 * G1 + P3 * P2 * P1 * G0) // /P = ~(P3 * P2 * P1 * P0) // // Timing values from the data sheet AC Characteristics table, // 54F/74F PRELIMINARY column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), // typical values only — Min/Max columns were left blank. // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f182 ( input wire g1_n, // Pin 1 — /G1 Carry Generate input 1 (active LOW) input wire p1_n, // Pin 2 — /P1 Carry Propagate input 1 (active LOW) input wire g0_n, // Pin 3 — /G0 Carry Generate input 0 (active LOW) input wire p0_n, // Pin 4 — /P0 Carry Propagate input 0 (active LOW) input wire g3_n, // Pin 5 — /G3 Carry Generate input 3 (active LOW) input wire p3_n, // Pin 6 — /P3 Carry Propagate input 3 (active LOW) output wire p_n, // Pin 7 — /P Carry Propagate output (active LOW) output wire cn_z, // Pin 9 — Cn+z Carry output z output wire g_n, // Pin 10 — /G Carry Generate output (active LOW) output wire cn_y, // Pin 11 — Cn+y Carry output y output wire cn_x, // Pin 12 — Cn+x Carry output x input wire cn, // Pin 13 — Cn Carry input input wire g2_n, // Pin 14 — /G2 Carry Generate input 2 (active LOW) input wire p2_n // Pin 15 — /P2 Carry Propagate input 2 (active LOW) ); wire g0 = ~g0_n, g1 = ~g1_n, g2 = ~g2_n, g3 = ~g3_n; wire p0 = ~p0_n, p1 = ~p1_n, p2 = ~p2_n, p3 = ~p3_n; assign cn_x = g0 | (p0 & cn); assign cn_y = g1 | (p1 & g0) | (p1 & p0 & cn); assign cn_z = g2 | (p2 & g1) | (p2 & p1 & g0) | (p2 & p1 & p0 & cn); assign g_n = ~(g3 | (p3 & g2) | (p3 & p2 & g1) | (p3 & p2 & p1 & g0)); assign p_n = ~(p3 & p2 & p1 & p0); specify // Propagation delays — typ values only (preliminary datasheet): // Cn to Cn+x/y/z: tPLH 4.6, tPHL 4.5 ns // Gn to Cn+x/y/z: tPLH 2.9, tPHL 2.8 ns (G0–G2 only) // Pn to Cn+x/y/z: tPLH 2.9, tPHL 2.8 ns (P0–P2 only) // Gn to /G: tPLH 4.5, tPHL 4.3 ns // Pn to /G: tPLH 4.5, tPHL 4.3 ns (P1–P3 only) // Pn to /P: tPLH 5.0, tPHL 4.8 ns specparam cn_tlh = 4.6, cn_thl = 4.5; specparam gpn_tlh = 2.9, gpn_thl = 2.8; specparam g_tlh = 4.5, g_thl = 4.3; specparam p_tlh = 5.0, p_thl = 4.8; // Cn to carry outputs (cn => cn_x) = (cn_tlh, cn_thl); (cn => cn_y) = (cn_tlh, cn_thl); (cn => cn_z) = (cn_tlh, cn_thl); // /G0 /G1 /G2 /P0 /P1 /P2 to carry outputs (g0_n, p0_n => cn_x) = (gpn_tlh, gpn_thl); (g0_n, p0_n, g1_n, p1_n => cn_y) = (gpn_tlh, gpn_thl); (g0_n, p0_n, g1_n, p1_n, g2_n, p2_n => cn_z) = (gpn_tlh, gpn_thl); // /G inputs to /G output (all four) (g0_n, g1_n, g2_n, g3_n => g_n) = (g_tlh, g_thl); // /P1 /P2 /P3 to /G output (p1_n, p2_n, p3_n => g_n) = (g_tlh, g_thl); // /Pn to /P output (all four) (p0_n, p1_n, p2_n, p3_n => p_n) = (p_tlh, p_thl); endspecify endmodule