DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (16-pin DIP) | TRUTH TABLE | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS
The 'F350 is a specialized multiplexer that accepts a 4-bit word and shifts it 0, 1, 2 or 3 places, as determined by two Select (S0, S1) inputs. For expansion to longer words, three linking inputs are provided for lower-order bits; thus two packages can shift an 8-bit word, four packages a 16-bit word, etc. Shifting by more than three places is accomplished by paralleling the 3-state outputs of different packages and using the Output Enable (/OE) inputs as a third Select level. With appropriate interconnections, the 'F350 can perform zero-backfill, sign-extend or end-around (barrel) shift functions. o Linking Inputs for Word Expansion o 3-State Outputs for Extending Shift Range
The 'F350 is operationally equivalent to a 4-input multiplexer with the
inputs connected so that the select code causes successive one-bit
shifts of the data word. This internal connection makes it possible to
perform shifts of 0, 1, 2 or 3 places on words of any length.
A 7-bit data word is introduced at the In inputs and is shifted
according to the code applied to the select inputs S0, S1. Outputs
O0-O3 are 3-state, controlled by an active LOW output enable (/OE). When
/OE is LOW, data outputs will follow selected data inputs; when HIGH,
the data outputs will be forced to the high impedance state. This
feature allows shifters to be cascaded on the same output lines or to a
common bus. The shift function can be logical, with zeros pulled in at
either or both ends of the shifting field; arithmetic, where the sign
bit is repeated during a shift down; or end around, where the data word
forms a continuous loop.
Logic equations
~~~~~~~~~~~~~~~
O0 = /S0*/S1*I0 + S0*/S1*I-1 + /S0*S1*I-2 + S0*S1*I-3
O1 = /S0*/S1*I1 + S0*/S1*I0 + /S0*S1*I-1 + S0*S1*I-2
O2 = /S0*/S1*I2 + S0*/S1*I1 + /S0*S1*I0 + S0*S1*I-1
O3 = /S0*/S1*I3 + S0*/S1*I2 + /S0*S1*I1 + S0*S1*I0
Pin Function Pin Function --- ----------------------- --- ----------------------- 1 I-3 Linking input -3 16 Vcc 2 I-2 Linking input -2 15 O0 Output 0 3 I-1 Linking input -1 14 O1 Output 1 4 I0 Data input 0 13 /OE Output Enable 5 I1 Data input 1 12 O2 Output 2 6 I2 Data input 2 11 O3 Output 3 7 I3 Data input 3 10 S0 Select input 0 8 GND 9 S1 Select input 1 I-3, I-2 and I-1 are the linking inputs that carry the three lower-order bits from the next package down when shifters are cascaded.
Inputs Outputs ------------ ------------------ /OE S1 S0 O0 O1 O2 O3 --- --- --- --- --- --- --- H X X Z Z Z Z L L L I0 I1 I2 I3 L L H I-1 I0 I1 I2 L H L I-2 I-1 I0 I1 L H H I-3 I-2 I-1 I0 H = HIGH voltage level; L = LOW voltage level; X = immaterial; Z = high impedance.
Pin Names Description U.L. HIGH/LOW ---------- -------------------------------- ------------- S0, S1 Select Inputs 0.5 / 0.75 I-3 - I3 Data Inputs 0.5 / 0.75 /OE Output Enable Input (Active LOW) 0.5 / 0.75 O0 - O3 3-State Outputs 75 / 15
Symbol Parameter Min Typ Max Units Conditions ------ -------------------- --- --- --- ----- ------------------------- ICCH Power Supply Current 22 35 mA Outputs HIGH, Vcc = Max ICCL Power Supply Current 27 41 mA Outputs LOW, Vcc = Max ICCZ Power Supply Current 26 42 mA Outputs OFF, Vcc = Max
TA = +25 C 74F
Vcc = +5.0V TA/Vcc = Com
Symbol Parameter CL Min Typ Max Min Max Units
------ ----------------------------- ----- --- ---- --- --- ---- -----
tPLH Prop Delay In to On 50 pF 3.0 4.5 6.0 3.0 7.0 ns
tPHL Prop Delay In to On 50 pF 2.5 4.0 5.5 2.5 6.5 ns
tPLH Prop Delay Sn to On 50 pF 4.0 7.8 10.0 4.0 11.0 ns
tPHL Prop Delay Sn to On 50 pF 3.0 6.5 8.5 3.0 9.5 ns
tPZH Output Enable Time 50 pF 2.5 5.0 7.0 2.5 8.0 ns
tPZL Output Enable Time 50 pF 4.0 7.0 9.0 4.0 10.0 ns
tPHZ Output Disable Time 50 pF 2.0 3.9 5.5 2.0 6.5 ns
tPLZ Output Disable Time 50 pF 2.0 4.0 5.5 2.0 6.5 ns
Data sheet transcription as plain text
No model for this device yet — only the data sheet transcription above.