DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (16-pin DIP) | TRUTH TABLE (each section) | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | VERILOG MODEL
The 'F158 is a high speed quad 2-input multiplexer. It selects four bits of data from two sources using the common Select and Enable inputs. The four buffered outputs present the selected data in the INVERTED form. The 'F158 can also generate any four of the 16 different functions of two variables.
The 'F158 is a quad 2-input multiplexer fabricated with the Schottky barrier diode process for high speed. It selects four bits of data from two sources under the control of a common Select input (S) and presents the data in INVERTED FORM at the four outputs. The Enable input (/E) is ACTIVE LOW. When /E is HIGH, all of the outputs (/Z) are forced HIGH regardless of all other inputs. The 'F158 is the logic implementation of a 4-POLE, 2-POSITION SWITCH where the position of the switch is determined by the logic levels supplied to the Select input. A common use is moving data from two groups of registers to four common output busses; the particular register from which the data comes is determined by the state of the Select input. A less obvious use is as a FUNCTION GENERATOR -- the 'F158 can generate four functions of two variables with one variable common, useful for implementing gating functions.
Pin Function Pin Function --- ---------------------- --- ------------------------------ 1 S Select input 16 Vcc 2 I0a Source 0, bit a 15 /E Enable input (active LOW) 3 I1a Source 1, bit a 14 I0c Source 0, bit c 4 /Za Inverted output a 13 I1c Source 1, bit c 5 I0b Source 0, bit b 12 /Zc Inverted output c 6 I1b Source 1, bit b 11 I0d Source 0, bit d 7 /Zb Inverted output b 10 I1d Source 1, bit d 8 GND 9 /Zd Inverted output d Pin-for-pin identical to the 'F157 except that the four outputs are inverted.
--- INPUTS --- OUTPUTS
/E S I0 I1 /Z
-- -- -- -- --
H X X X H
L L L X H
L L H X L
L H X L H
L H X H L
H = HIGH voltage level; L = LOW voltage level; X = immaterial.
Summary: S = LOW selects the I0 inputs; S = HIGH selects the I1
inputs; the selected data appears inverted at /Z.
The table applies to each of the four sections a, b, c, d: read I0 as
I0a ... I0d, I1 as I1a ... I1d and /Z as /Za ... /Zd. S and /E are
common to all four sections.
Pin Names Description U.L. HIGH/LOW ----------- ------------------------- ------------- I0a - I0d Source 0 Data Inputs 0.5 / 0.375 I1a - I1d Source 1 Data Inputs 0.5 / 0.375 /E Enable Input (Active LOW) 0.5 / 0.375 S Select Input 0.5 / 0.375 /Za - /Zd Inverted Outputs 25 / 12.5
Symbol Parameter Min Typ Max Units Conditions ------ -------------------- --- --- --- ----- ------------- ICC Power Supply Current 10 mA Vcc = Max * *ICC measured with outputs open and 4.5 V applied to all inputs.
Symbol Parameter Min Typ Max Units ------ -------------------------- --- --- --- ----- tPLH Propagation Delay S to /Z -- 6.3 -- ns tPHL Propagation Delay S to /Z -- 6.2 -- ns tPLH Propagation Delay /E to /Z -- 4.6 -- ns tPHL Propagation Delay /E to /Z -- 4.5 -- ns tPLH Propagation Delay In to /Z -- 2.9 -- ns tPHL Propagation Delay In to /Z -- 2.8 -- ns
Data sheet transcription as plain text
// ============================================================================ // f158.v — 54F/74F158 Quad 2-Input Multiplexer (Inverting) // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F158.txt (1980 Fairchild FAST Data Book, // pages 4-25 ... 4-26) — PRELIMINARY data sheet // // Four 2-input multiplexers with a common Select input (S) and a common // active-LOW Enable (e_n); pin-for-pin identical to the 'F157 except that // the outputs are INVERTED. S LOW selects the I0 (source 0) inputs, S HIGH // selects the I1 (source 1) inputs; the selected data appears inverted at // Z_n. When e_n is HIGH, all outputs are forced HIGH regardless of all // other inputs. // // zn_n = e_n | ~(s ? i1n : i0n) // // Timing values from the data sheet AC Characteristics table, // 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF). The sheet is // preliminary: only TYPICAL values are given (min/max columns blank), so // every specparam carries the typ value only. // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f158 ( input wire s, // select input (common) input wire e_n, // enable input (active LOW) input wire i0a, i1a, // source 0/1 data inputs, bit a output wire za_n, // inverted output a input wire i0b, i1b, // source 0/1 data inputs, bit b output wire zb_n, // inverted output b input wire i0c, i1c, // source 0/1 data inputs, bit c output wire zc_n, // inverted output c input wire i0d, i1d, // source 0/1 data inputs, bit d output wire zd_n // inverted output d ); assign za_n = e_n | ~(s ? i1a : i0a); assign zb_n = e_n | ~(s ? i1b : i0b); assign zc_n = e_n | ~(s ? i1c : i0c); assign zd_n = e_n | ~(s ? i1d : i0d); specify // All values TYP only (preliminary data sheet; min/max columns // left blank), 54F/74F +25 C 5.0 V C_L = 15 pF. // Propagation delay S to Z_n (data sheet: typ 6.3 / 6.2 ns) specparam tlh_s_z = 6.3; specparam thl_s_z = 6.2; // Propagation delay E_n to Z_n (data sheet: typ 4.6 / 4.5 ns) specparam tlh_e_z = 4.6; specparam thl_e_z = 4.5; // Propagation delay I_n to Z_n (data sheet: typ 2.9 / 2.8 ns) specparam tlh_i_z = 2.9; specparam thl_i_z = 2.8; (s => za_n) = (tlh_s_z, thl_s_z); (s => zb_n) = (tlh_s_z, thl_s_z); (s => zc_n) = (tlh_s_z, thl_s_z); (s => zd_n) = (tlh_s_z, thl_s_z); (e_n => za_n) = (tlh_e_z, thl_e_z); (e_n => zb_n) = (tlh_e_z, thl_e_z); (e_n => zc_n) = (tlh_e_z, thl_e_z); (e_n => zd_n) = (tlh_e_z, thl_e_z); (i0a, i1a => za_n) = (tlh_i_z, thl_i_z); (i0b, i1b => zb_n) = (tlh_i_z, thl_i_z); (i0c, i1c => zc_n) = (tlh_i_z, thl_i_z); (i0d, i1d => zd_n) = (tlh_i_z, thl_i_z); endspecify endmodule