DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (20-pin DIP) | MODE SELECT TABLE | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | AC OPERATING REQUIREMENTS
The 'F322 is an 8-bit shift register with provision for either serial or parallel loading and with 3-state parallel outputs plus a bi-state serial output. Parallel data inputs and parallel outputs are multiplexed to minimize pin count. State changes are initiated by the rising edge of the clock. Four synchronous modes of operation are possible: hold (store), shift right with serial entry, shift right with sign extend and parallel load. An asynchronous Master Reset (/MR) input overrides clocked operation and clears the register. o Multiplexed Parallel I/O Ports o Separate Serial Input and Output o Sign Extend Function o 3-State Outputs for Bus Applications
The 'F322 contains eight D-type edge triggered flip-flops and the interstage gating required to perform right shift and the intrastage gating necessary for hold and synchronous parallel load operations. A LOW signal on /RE enables shifting or parallel loading, while a HIGH signal enables the hold mode. A HIGH signal on S//P enables shift right, while a LOW signal disables the 3-state output buffers and enables parallel loading. In the shift right mode a HIGH signal on /SE enables serial entry from either D0 or D1, as determined by the S input. A LOW signal on /SE enables shift right but Q7 reloads its contents, thus performing the sign extend function required for the 'F384 Twos Complement Multiplier. A HIGH signal on /OE disables the 3-state output buffers, regardless of the other control inputs. In this condition the shifting and loading operations can still be performed.
Pin Function Pin Function --- --------------------------- --- --------------------------- 1 /RE Register Enable 20 Vcc 2 S//P Serial/Parallel Mode 19 S Serial Data Select 3 D0 Serial Data input 0 18 /SE Sign Extend 4 I/O7 Parallel I/O bit 7 17 D1 Serial Data input 1 5 I/O5 Parallel I/O bit 5 16 I/O6 Parallel I/O bit 6 6 I/O3 Parallel I/O bit 3 15 I/O4 Parallel I/O bit 4 7 I/O1 Parallel I/O bit 1 14 I/O2 Parallel I/O bit 2 8 /OE Output Enable 13 I/O0 Parallel I/O bit 0 9 /MR Master Reset 12 Q0 Serial output 10 GND 11 CP Clock Pulse The odd-numbered I/O pins are on the left side of the package and the even-numbered ones on the right, so I/O0 - I/O7 are not in pin order.
Inputs Outputs
------------------------------ ---------------------------------------
Mode /MR /RE S//P /SE S /OE* CP I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Q0
----------- --- --- ---- --- - ---- --- ---- ---- ---- ---- ---- ---- ---- ---- --
Clear L X X X X L X L L L L L L L L L
L X X X X H X Z Z Z Z Z Z Z Z L
Parallel H L L X X X ^ I7 I6 I5 I4 I3 I2 I1 I0 I0
Load
Shift Right H L H H L L ^ D0 O7 O6 O5 O4 O3 O2 O1 O1
H L H H H L ^ D1 O7 O6 O5 O4 O3 O2 O1 O1
Sign Extend H L H L X L ^ O7 O7 O6 O5 O4 O3 O2 O1 O1
Hold H H X X X L ^ NC NC NC NC NC NC NC NC NC
*When the /OE input is HIGH all I/On terminals are at the high impedance
state; sequential operation or clearing of the register is not affected.
1. I7-I0 = The level of the steady-state input at the respective I/O
terminal is loaded into the flip-flop while the flip-flop outputs
(except Q0) are isolated from the I/O terminal.
2. D0, D1 = The level of the steady-state inputs to the serial
multiplexer input.
3. O7-O0 = The level of the respective Qn flip-flop prior to the last
Clock LOW-to-HIGH transition.
H = HIGH voltage level; L = LOW voltage level; X = immaterial.
Z = high impedance output state; NC = no change.
^ = LOW-to-HIGH transition of CP.
Pin Names Description U.L. HIGH/LOW
------------ -------------------------------------------- -------------
/RE Register Enable Input (Active LOW) 0.5 / 0.375
S//P Serial (HIGH) or Parallel (LOW) Mode Control 0.5 / 0.375
Input
/SE Sign Extend Input (Active LOW) 0.5 / 1.125
S Serial Data Select Input 0.5 / 0.75
D0, D1 Serial Data Inputs 0.5 / 0.375
CP Clock Pulse Input (Active Rising Edge) 0.5 / 0.375
/MR Asynchronous Master Reset Input (Active LOW) 0.5 / 0.375
/OE 3-State Output Enable Input (Active LOW) 0.5 / 0.375
Q0 Bi-state Serial Output 25 / 12.5
I/O0 - I/O7 Multiplexed Parallel Data Inputs or 1.75 / 0.406
3-State Parallel Data Outputs 25 / 12.5
Symbol Parameter Min Typ Max Units Conditions
------ -------------------- --- --- --- ----- --------------------
ICC Power Supply Current 60 90 mA Vcc = Max, CP = HIGH
Output Disabled
TA = +25 C 74F
Vcc = +5.0V TA/Vcc = Com
Symbol Parameter CL Min Typ Max Min Max Units
------ ----------------------------- ----- --- ---- --- --- ---- -----
fmax Maximum Clock Frequency -- 70 90 -- 70 -- MHz
tPLH Prop Delay CP to I/On 50 pF 3.5 5.5 7.5 3.5 8.5 ns
tPHL Prop Delay CP to I/On 50 pF 4.0 6.0 8.0 3.5 9.0 ns
tPLH Prop Delay CP to Q0 50 pF 3.5 7.0 9.0 3.5 10.0 ns
tPHL Prop Delay CP to Q0 50 pF 3.5 6.0 8.0 3.5 9.0 ns
tPHL Prop Delay /MR to I/On 50 pF 6.0 10.0 13.0 6.0 14.0 ns
tPHL Prop Delay /MR to Q0 50 pF 5.5 9.5 12.0 5.5 13.0 ns
tPZH Output Enable Time /OE to 50 pF 3.0 6.5 9.0 3.0 10.0 ns
I/On
tPZL Output Enable Time /OE to 50 pF 4.0 8.5 11.0 4.0 12.0 ns
I/On
tPHZ Output Disable Time /OE to 50 pF 2.0 4.5 6.0 2.0 7.0 ns
I/On
tPLZ Output Disable Time /OE to 50 pF 2.0 5.0 7.0 2.0 8.0 ns
I/On
tPZH Output Enable Time S//P to 50 pF 4.5 8.0 10.5 4.5 11.5 ns
I/On
tPZL Output Enable Time S//P to 50 pF 5.5 10.0 14.0 5.5 15.0 ns
I/On
tPHZ Output Disable Time S//P to 50 pF 5.0 9.0 11.5 5.0 12.5 ns
I/On
tPLZ Output Disable Time S//P to 50 pF 6.0 12.0 15.5 6.0 16.5 ns
I/On
TA = +25 C 74F
Vcc = +5.0V TA/Vcc = Com
Symbol Parameter Min Typ Max Min Max Units
------ -------------------------------------- --- --- --- --- --- -----
ts (H) Setup Time, HIGH -- /RE to CP 6.0 -- -- 7.0 -- ns
ts (L) Setup Time, LOW -- /RE to CP 14.0 -- -- 16.0 -- ns
th (H) Hold Time, HIGH -- /RE to CP 0 -- -- 0 -- ns
th (L) Hold Time, LOW -- /RE to CP 0 -- -- 0 -- ns
ts (H) Setup Time, HIGH -- D0, D1 or I/On to CP 6.5 -- -- 7.5 -- ns
ts (L) Setup Time, LOW -- D0, D1 or I/On to CP 6.5 -- -- 7.5 -- ns
th (H) Hold Time, HIGH -- D0, D1 or I/On to CP 2.0 -- -- 3.0 -- ns
th (L) Hold Time, LOW -- D0, D1 or I/On to CP 2.0 -- -- 3.0 -- ns
ts (H) Setup Time, HIGH -- /SE to CP 7.0 -- -- 8.0 -- ns
ts (L) Setup Time, LOW -- /SE to CP 2.5 -- -- 3.5 -- ns
th (H) Hold Time, HIGH -- /SE to CP 2.0 -- -- 2.0 -- ns
th (L) Hold Time, LOW -- /SE to CP 0 -- -- 0 -- ns
ts (H) Setup Time, HIGH -- S//P to CP 11.0 -- -- 12.0 -- ns
ts (L) Setup Time, LOW -- S//P to CP 13.5 -- -- 15.5 -- ns
ts (H) Setup Time, HIGH -- S to CP 6.5 -- -- 7.5 -- ns
ts (L) Setup Time, LOW -- S to CP 9.0 -- -- 10.0 -- ns
th (H) Hold Time, HIGH -- S or S//P to CP 0 -- -- 0 -- ns
th (L) Hold Time, LOW -- S or S//P to CP 0 -- -- 0 -- ns
tw (H) CP Pulse Width, HIGH 7.0 -- -- 7.0 -- ns
tw (L) /MR Pulse Width, LOW 5.5 -- -- 6.5 -- ns
trec Recovery Time /MR to CP 8.0 -- -- 8.0 -- ns
Data sheet transcription as plain text
No model for this device yet — only the data sheet transcription above.