74F382

4-BIT ARITHMETIC LOGIC UNIT


Family
Fairchild FAST (Advanced Schottky TTL)
Source
1985 Fairchild FAST Data Book, pages 4-249 ... 4-253. The 1980 data book carries the 'F382 in its Section 3 selection guide only (page 3-34, description and logic symbol).
Status
Released data sheet
Ratings
Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C

DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (20-pin DIP) | FUNCTION SELECT TABLE | TRUTH TABLE | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS

DESCRIPTION

The 'F382 performs three arithmetic and three logic operations on two
4-bit words, A and B. Two additional Select input codes force the
Function outputs LOW or HIGH. An Overflow output is provided for
convenience in twos complement arithmetic. A Carry output is provided
for ripple expansion. For high-speed expansion using a Carry Lookahead
Generator, refer to the 'F381 data sheet.

  o Performs Six Arithmetic and Logic Functions
  o Selectable LOW (Clear) and HIGH (Preset) Functions
  o LOW Input Loading Minimizes Drive Requirements
  o Carry Output for Ripple Expansion
  o Overflow Output for Twos Complement Arithmetic

FUNCTIONAL DESCRIPTION

Signals applied to the Select inputs S0-S2 determine the mode of
operation, as indicated in the Function Select Table. An extensive
listing of input and output levels is shown in the Truth Table. The
circuit performs the arithmetic functions for either active HIGH or
active LOW operands, with output levels in the same convention. In the
Subtract operating modes, it is necessary to force a carry (HIGH for
active HIGH operands, LOW for active LOW operands) into the Cn input of
the least significant package. Ripple expansion is illustrated in Figure
a. The overflow output OVR is the Exclusive-OR of Cn+3 and Cn+4; a HIGH
signal on OVR indicates overflow in twos complement operation. Typical
delays for Figure a are given in Figure b.

CONNECTION DIAGRAM (20-pin DIP)

Pin  Function                  Pin  Function
---  ------------------------  ---  ------------------------
  1  A1    A operand input 1    20  Vcc
  2  B1    B operand input 1    19  A2    A operand input 2
  3  A0    A operand input 0    18  B2    B operand input 2
  4  B0    B operand input 0    17  A3    A operand input 3
  5  S0    Function Select 0    16  B3    B operand input 3
  6  S1    Function Select 1    15  Cn    Carry input
  7  S2    Function Select 2    14  Cn+4  Carry output
  8  F0    Function output 0    13  OVR   Overflow output
  9  F1    Function output 1    12  F3    Function output 3
 10  GND                        11  F2    Function output 2

FUNCTION SELECT TABLE

 Select
----------
S0  S1  S2   Operation
--  --  --   -----------
 L   L   L   Clear
 H   L   L   B Minus A
 L   H   L   A Minus B
 H   H   L   A Plus B

 L   L   H   A xor B
 H   L   H   A + B
 L   H   H   AB
 H   H   H   Preset

H = HIGH voltage level;  L = LOW voltage level.

TRUTH TABLE

                    Inputs              Outputs
              ------------------  --------------------------
Function      S0 S1 S2  Cn An Bn  F0 F1 F2 F3   OVR   Cn+4
------------  --------  --------  -----------  -----  -----
CLEAR          0  0  0   0  X  X   0  0  0  0    1      1
                         1  X  X   0  0  0  0    1      1

B MINUS A      1  0  0   0  0  0   1  1  1  1    0      0
                         0  0  1   0  0  0  0    0      1
                         0  1  0   0  0  0  0    0      0
                         0  1  1   1  1  1  1    0      0
                         1  0  0   0  0  0  0    0      1
                         1  0  1   1  1  1  1    0      1
                         1  1  0   1  0  0  0    0      0
                         1  1  1   0  0  0  0    0      1

A MINUS B      0  1  0   0  0  0   1  1  1  1    0      0
                         0  0  1   0  0  0  0    0      0
                         0  1  0   0  1  1  1    0      1
                         0  1  1   1  1  1  1    0      0
                         1  0  0   0  0  0  0    0      1
                         1  0  1   1  0  0  0    0      0
                         1  1  0   1  1  1  1    0      1
                         1  1  1   0  0  0  0    0      1

A PLUS B       1  1  0   0  0  0   0  0  0  0    0      0
                         0  0  1   1  1  1  1    0      0
                         0  1  0   1  1  1  1    0      0
                         0  1  1   0  1  1  1    0      1
                         1  0  0   1  0  0  0    0      0
                         1  0  1   0  0  0  0    0      1
                         1  1  0   0  0  0  0    0      1
                         1  1  1   1  1  1  1    0      1

A xor B        0  0  1   X  0  0   0  0  0  0    0      0
                         X  0  1   1  1  1  1    0      0
                         0  1  0   1  1  1  1    0      0
                         X  1  1   0  0  0  0    1      1
                         1  1  0   1  1  1  1    1      1

A + B          1  0  1   X  0  0   0  0  0  0    0      0
                         X  0  1   1  1  1  1    0      0
                         X  1  0   1  1  1  1    0      0
                         0  1  1   1  1  1  1    0      0
                         1  1  1   1  1  1  1    1      1

AB             0  1  1   X  0  0   0  0  0  0    1      1
                         X  0  1   0  0  0  0    0      0
                         X  1  0   0  0  0  0    1      1
                         0  1  1   1  1  1  1    0      0
                         1  1  1   1  1  1  1    1      1

PRESET         1  1  1   X  0  0   1  1  1  1    0      0
                         X  0  1   1  1  1  1    0      0
                         X  1  0   1  1  1  1    0      0
                         0  1  1   1  1  1  1    0      0
                         1  1  1   1  1  1  1    1      1

1 = HIGH voltage level;  0 = LOW voltage level;  X = immaterial.

INPUT LOADING / FAN-OUT

Pin Names   Description             U.L. HIGH/LOW
----------  ----------------------  -------------
A0 - A3     A Operand Inputs        0.5 / 1.50
B0 - B3     B Operand Inputs        0.5 / 1.50
S0 - S2     Function Select Inputs  0.5 / 0.375
Cn          Carry Input             0.5 / 1.875
Cn+4        Carry Output            25 / 12.5
OVR         Overflow Output         25 / 12.5
F0 - F3     Function Outputs        25 / 12.5

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE

Symbol  Parameter             Min  Typ  Max  Units  Conditions
------  --------------------  ---  ---  ---  -----  -----------------------
ICC     Power Supply Current        54   81  mA     Vcc = Max; S0, Cn = HIGH
                                                    Other Inputs Gnd

AC CHARACTERISTICS

                                              TA = +25 C      74F
                                              Vcc = +5.0V     TA/Vcc = Com
Symbol  Parameter                      CL     Min  Typ   Max  Min  Max   Units
------  -----------------------------  -----  ---  ----  ---  ---  ----  -----
tPLH    Prop Delay Cn to Fi            50 pF  3.0   8.1 12.0  3.0  13.0  ns
tPHL    Prop Delay Cn to Fi            50 pF  2.5   5.7  8.0  2.5   9.0  ns
tPLH    Prop Delay Any A or B to       50 pF  4.0  10.4 15.0  4.0  16.0  ns
          Any F
tPHL    Prop Delay Any A or B to       50 pF  3.5   8.2 11.0  3.5  12.0  ns
          Any F
tPLH    Prop Delay Si to Fi            50 pF  6.5  11.0 15.0  6.5  16.0  ns
tPHL    Prop Delay Si to Fi            50 pF  4.0   8.2 20.5  4.0  21.5  ns
tPLH    Prop Delay Ai or Bi to Cn+4    50 pF  3.5   6.0  8.5  3.5   9.5  ns
tPHL    Prop Delay Ai or Bi to Cn+4    50 pF  3.5   6.5  9.0  3.5  10.5  ns
tPLH    Prop Delay Si to OVR or Cn+4   50 pF  7.0  12.5 16.5  7.0  17.5  ns
tPHL    Prop Delay Si to OVR or Cn+4   50 pF  5.0   9.0 12.0  5.0  13.0  ns
tPLH    Prop Delay Cn to Cn+4          50 pF  3.5   5.6  8.0  3.5   9.0  ns
tPHL    Prop Delay Cn to Cn+4          50 pF  3.5   6.3  9.0  3.5  10.0  ns
tPLH    Prop Delay Cn to OVR           50 pF  3.5   8.0 11.0  3.5  12.0  ns
tPHL    Prop Delay Cn to OVR           50 pF  4.5   7.1 10.0  4.5  11.0  ns
tPLH    Prop Delay Ai or Bi to OVR     50 pF  7.0  11.5 15.5  7.0  16.5  ns
tPHL    Prop Delay Ai or Bi to OVR     50 pF  5.5   8.0 10.5  5.5  11.5  ns

Data sheet transcription as plain text

VERILOG MODEL

No model for this device yet — only the data sheet transcription above.


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