======================================================================== 74F158 QUAD 2-INPUT MULTIPLEXER ======================================================================== Family: Fairchild FAST (Advanced Schottky TTL) Source: 1980 Fairchild FAST Data Book, pages 4-25 ... 4-26 Status: PRELIMINARY -- page 4-25 carries a "Preliminary" watermark. Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C DESCRIPTION ----------- The 'F158 is a high speed quad 2-input multiplexer. It selects four bits of data from two sources using the common Select and Enable inputs. The four buffered outputs present the selected data in the INVERTED form. The 'F158 can also generate any four of the 16 different functions of two variables. FUNCTIONAL DESCRIPTION ---------------------- The 'F158 is a quad 2-input multiplexer fabricated with the Schottky barrier diode process for high speed. It selects four bits of data from two sources under the control of a common Select input (S) and presents the data in INVERTED FORM at the four outputs. The Enable input (/E) is ACTIVE LOW. When /E is HIGH, all of the outputs (/Z) are forced HIGH regardless of all other inputs. The 'F158 is the logic implementation of a 4-POLE, 2-POSITION SWITCH where the position of the switch is determined by the logic levels supplied to the Select input. A common use is moving data from two groups of registers to four common output busses; the particular register from which the data comes is determined by the state of the Select input. A less obvious use is as a FUNCTION GENERATOR -- the 'F158 can generate four functions of two variables with one variable common, useful for implementing gating functions. CONNECTION DIAGRAM (16-pin DIP) ------------------------------- Pin Function Pin Function --- ---------------------- --- ------------------------------ 1 S Select input 16 Vcc 2 I0a Source 0, bit a 15 /E Enable input (active LOW) 3 I1a Source 1, bit a 14 I0c Source 0, bit c 4 /Za Inverted output a 13 I1c Source 1, bit c 5 I0b Source 0, bit b 12 /Zc Inverted output c 6 I1b Source 1, bit b 11 I0d Source 0, bit d 7 /Zb Inverted output b 10 I1d Source 1, bit d 8 GND 9 /Zd Inverted output d Pin-for-pin identical to the 'F157 except that the four outputs are inverted. TRUTH TABLE (each section) -------------------------- --- INPUTS --- OUTPUTS /E S I0 I1 /Z -- -- -- -- -- H X X X H L L L X H L L H X L L H X L H L H X H L H = HIGH voltage level; L = LOW voltage level; X = immaterial. Summary: S = LOW selects the I0 inputs; S = HIGH selects the I1 inputs; the selected data appears inverted at /Z. The table applies to each of the four sections a, b, c, d: read I0 as I0a ... I0d, I1 as I1a ... I1d and /Z as /Za ... /Zd. S and /E are common to all four sections. INPUT LOADING / FAN-OUT ----------------------- Pin Names Description U.L. HIGH/LOW ----------- ------------------------- ------------- I0a - I0d Source 0 Data Inputs 0.5 / 0.375 I1a - I1d Source 1 Data Inputs 0.5 / 0.375 /E Enable Input (Active LOW) 0.5 / 0.375 S Select Input 0.5 / 0.375 /Za - /Zd Inverted Outputs 25 / 12.5 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE --------------------------------------------------- Symbol Parameter Min Typ Max Units Conditions ------ -------------------- --- --- --- ----- ------------- ICC Power Supply Current 10 mA Vcc = Max * *ICC measured with outputs open and 4.5 V applied to all inputs. AC CHARACTERISTICS ------------------ Symbol Parameter Min Typ Max Units ------ -------------------------- --- --- --- ----- tPLH Propagation Delay S to /Z -- 6.3 -- ns tPHL Propagation Delay S to /Z -- 6.2 -- ns tPLH Propagation Delay /E to /Z -- 4.6 -- ns tPHL Propagation Delay /E to /Z -- 4.5 -- ns tPLH Propagation Delay In to /Z -- 2.9 -- ns tPHL Propagation Delay In to /Z -- 2.8 -- ns