======================================================================== 74F194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER ======================================================================== Family: Fairchild FAST (Advanced Schottky TTL) Source: 1980 Fairchild FAST Data Book, pages 4-65 ... 4-67 Status: Released data sheet Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C DESCRIPTION ----------- The 'F194 is a high speed 4-bit bidirectional universal shift register. As a high speed multifunctional sequential building block, it is useful in a wide variety of applications. It may be used in serial-serial, shift left, shift right, serial-parallel, parallel-serial, and parallel-parallel data register transfers. The 'F194 is similar in operation to the 'S195 universal shift register, with added features of shift left without external connections and hold (do nothing) modes of operation. o TYPICAL SHIFT FREQUENCY OF 150 MHz o ASYNCHRONOUS MASTER RESET o HOLD (DO NOTHING) MODE o FULLY SYNCHRONOUS SERIAL OR PARALLEL DATA TRANSFERS FUNCTIONAL DESCRIPTION ---------------------- The 'F194 contains four edge-triggered D flip-flops and the necessary interstage logic to synchronously perform shift right, shift left, parallel load and hold operations. Signals applied to the Select (S0, S1) inputs determine the type of operation, as shown in the Mode Select Table. Signals on the Select, Parallel data (P0 - P3) and Serial data (DSR, DSL) inputs can change when the clock is in either state, provided only that the recommended setup and hold times, with respect to the clock rising edge, are observed. A LOW signal on Master Reset (/MR) overrides all other inputs and forces the outputs LOW. CONNECTION DIAGRAM (16-pin DIP) ------------------------------- The pin descriptions run long, so the two-up diagram is given as the two sides of the package in turn. Pins 1 - 8, left side of the package: Pin Function --- ------------------------------------------- 1 /MR Asynchronous Master Reset (active LOW) 2 DSR Serial Data Input (Shift Right) 3 P0 Parallel data input 0 4 P1 Parallel data input 1 5 P2 Parallel data input 2 6 P3 Parallel data input 3 7 DSL Serial Data Input (Shift Left) 8 GND Pins 16 - 9, right side of the package: Pin Function --- ------------------------------------------- 16 Vcc 15 Q0 Parallel output 0 14 Q1 Parallel output 1 13 Q2 Parallel output 2 12 Q3 Parallel output 3 11 CP Clock Pulse (active rising edge) 10 S1 Mode Control input 1 9 S0 Mode Control input 0 MODE SELECT TABLE ----------------- Operating Mode /MR S1 S0 DSR DSL Pn Q0 Q1 Q2 Q3 -------------- --- --- --- --- --- --- --- --- --- --- Reset L X X X X X L L L L Hold H l l X X X q0 q1 q2 q3 Shift Left H h l X l X q1 q2 q3 L Shift Left H h l X h X q1 q2 q3 H Shift Right H l h l X X L q0 q1 q2 Shift Right H l h h X X H q0 q1 q2 Parallel Load H h h X X pn p0 p1 p2 p3 l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition. h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition. pn (qn) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition. H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial INPUT LOADING / FAN-OUT ----------------------- Pin Names Description U.L. HIGH/LOW --------- -------------------------------------------- ------------- S0, S1 Mode Control Inputs 0.5 / 0.375 P0 - P3 Parallel Data Inputs 0.5 / 0.375 DSR Serial Data Input (Shift Right) 0.5 / 0.375 DSL Serial Data Input (Shift Left) 0.5 / 0.375 CP Clock Pulse Input (Active Rising Edge) 0.5 / 0.375 /MR Asynchronous Master Reset Input (Active LOW) 0.5 / 0.375 Q0 - Q3 Parallel Outputs 25 / 12.5 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE --------------------------------------------------- Conditions for all rows: Vcc = Max; Sn, /MR, DSR, DSL = 4.5 V; Pn = Gnd; CP = ^ (rising edge). Symbol Parameter Min Typ Max Units ------ -------------------- --- --- --- ----- ICC Power Supply Current 33 46 mA AC CHARACTERISTICS ------------------ Symbol Parameter Min Typ Max Units ------ --------------------------- --- --- --- ----- fmax Maximum Shift Frequency 105 150 -- MHz tPLH Propagation Delay CP to Qn 2.0 4.0 7.0 ns tPHL Propagation Delay CP to Qn 2.0 4.5 9.0 ns tPHL Propagation Delay /MR to Qn 5.0 10 13 ns AC OPERATING REQUIREMENTS ------------------------- Symbol Parameter Min Typ Max Units ------ ---------------------------------------- --- --- --- ----- ts (H) Setup Time, HIGH -- Pn, DSR or DSL to CP 4.0 -- -- ns ts (L) Setup Time, LOW -- Pn, DSR or DSL to CP 4.0 -- -- ns th (H) Hold Time, HIGH -- Pn, DSR or DSL to CP 0 -- -- ns th (L) Hold Time, LOW -- Pn, DSR or DSL to CP 0 -- -- ns ts (H) Setup Time, HIGH -- Sn to CP 8.0 -- -- ns ts (L) Setup Time, LOW -- Sn to CP 8.0 -- -- ns th (H) Hold Time, HIGH -- Sn to CP 0 -- -- ns th (L) Hold Time, LOW -- Sn to CP 0 -- -- ns tw (H) CP Pulse Width HIGH 5.0 -- -- ns tw (L) /MR Pulse Width LOW 5.0 -- -- ns trec Recovery Time -- /MR to CP 7.0 -- -- ns