// ============================================================================
// f539.v — 54F/74F539 Dual 1-of-4 Decoder (With 3-State Outputs)
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F539.txt (1980 Fairchild FAST Data Book,
//         pages 4-118 ... 4-120) — PRELIMINARY data sheet.
//
// Two independent one-of-four decoders, each with two active-HIGH address
// inputs and four mutually exclusive 3-state outputs.
//   - Polarity control P: P = L -> active-HIGH outputs (selected output
//     HIGH, others LOW); P = H -> active-LOW outputs (selected output LOW,
//     others HIGH).
//   - Enable E_n active LOW; when HIGH all four outputs of that half equal
//     the P input, so E_n serves as the data input when demultiplexing.
//   - OE_n HIGH forces that half's outputs to the high-impedance state.
//
// Suffixes a and b name the two halves, matching the data sheet pin names.
//
// Timing values from the data sheet AC Characteristics table
// (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF). The preliminary sheet gives
// TYP ONLY (min/max columns blank).
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f539 (
    input  wire a0a, a1a,               // side A address inputs (active HIGH)
    input  wire ea_n,                   // side A enable input (active LOW)
    input  wire oea_n,                  // side A output enable (active LOW)
    input  wire pa,                     // side A polarity control input
    output wire o0a, o1a, o2a, o3a,     // side A 3-state outputs 0-3
    input  wire a0b, a1b,               // side B address inputs (active HIGH)
    input  wire eb_n,                   // side B enable input (active LOW)
    input  wire oeb_n,                  // side B output enable (active LOW)
    input  wire pb,                     // side B polarity control input
    output wire o0b, o1b, o2b, o3b      // side B 3-state outputs 0-3
);

    wire [3:0] dec_a, dec_b;

    // One-hot decode, gated by the active-LOW enable. Each output is the
    // AND of both address bits against its own code (matching f138/f139's
    // construction) rather than a single indexed bit-select write: an
    // indexed write with an x-valued address index (`dec_a[addr_a] = 1'b1`)
    // is silently dropped by Verilog's bit-select semantics, which would
    // read as "disabled" instead of propagating the x. Written this way, an
    // x on an address bit only reaches the (at most two) outputs whose code
    // still matches the known bits.
    assign dec_a[0] = ~ea_n & ~a1a & ~a0a;
    assign dec_a[1] = ~ea_n & ~a1a &  a0a;
    assign dec_a[2] = ~ea_n &  a1a & ~a0a;
    assign dec_a[3] = ~ea_n &  a1a &  a0a;

    assign dec_b[0] = ~eb_n & ~a1b & ~a0b;
    assign dec_b[1] = ~eb_n & ~a1b &  a0b;
    assign dec_b[2] = ~eb_n &  a1b & ~a0b;
    assign dec_b[3] = ~eb_n &  a1b &  a0b;

    // Polarity control (XOR): selected output is ~P, all others P.
    // OE_n HIGH forces the high-impedance state.
    assign o0a = oea_n ? 1'bz : (dec_a[0] ^ pa);
    assign o1a = oea_n ? 1'bz : (dec_a[1] ^ pa);
    assign o2a = oea_n ? 1'bz : (dec_a[2] ^ pa);
    assign o3a = oea_n ? 1'bz : (dec_a[3] ^ pa);

    assign o0b = oeb_n ? 1'bz : (dec_b[0] ^ pb);
    assign o1b = oeb_n ? 1'bz : (dec_b[1] ^ pb);
    assign o2b = oeb_n ? 1'bz : (dec_b[2] ^ pb);
    assign o3b = oeb_n ? 1'bz : (dec_b[3] ^ pb);

    specify
        // Propagation delay A_n to O_n (data sheet, TYP ONLY — preliminary
        // sheet, min/max blank: tPLH 12.5, tPHL 11.5 ns)
        specparam tlh_a_o  = 12.5;
        specparam thl_a_o  = 11.5;

        // Propagation delay E_n to O_n (data sheet, TYP ONLY: tPLH 11.5,
        // tPHL 11 ns)
        specparam tlh_e_o  = 11.5;
        specparam thl_e_o  = 11.0;

        // Propagation delay P to O_n (data sheet, TYP ONLY: tPLH 13,
        // tPHL 12 ns)
        specparam tlh_p_o  = 13.0;
        specparam thl_p_o  = 12.0;

        // Output enable/disable time OE_n to O_n (data sheet, TYP ONLY:
        // tPZH 5.0, tPZL 5.5, tPHZ 5.0, tPLZ 5.0 ns; disable times
        // measured with C_L = 5 pF)
        specparam tzh_oe_o = 5.0;
        specparam tzl_oe_o = 5.5;
        specparam thz_oe_o = 5.0;
        specparam tlz_oe_o = 5.0;

        (a0a, a1a => o0a) = (tlh_a_o, thl_a_o);
        (a0a, a1a => o1a) = (tlh_a_o, thl_a_o);
        (a0a, a1a => o2a) = (tlh_a_o, thl_a_o);
        (a0a, a1a => o3a) = (tlh_a_o, thl_a_o);

        (ea_n => o0a) = (tlh_e_o, thl_e_o);
        (ea_n => o1a) = (tlh_e_o, thl_e_o);
        (ea_n => o2a) = (tlh_e_o, thl_e_o);
        (ea_n => o3a) = (tlh_e_o, thl_e_o);

        // 6-delay form, IEEE order (0->1, 1->0, 0->Z, Z->1, 1->Z, Z->0):
        // P causes only 0->1/1->0 transitions, OE_n only Z transitions.
        (oea_n, pa => o0a) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oea_n, pa => o1a) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oea_n, pa => o2a) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oea_n, pa => o3a) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);

        (a0b, a1b => o0b) = (tlh_a_o, thl_a_o);
        (a0b, a1b => o1b) = (tlh_a_o, thl_a_o);
        (a0b, a1b => o2b) = (tlh_a_o, thl_a_o);
        (a0b, a1b => o3b) = (tlh_a_o, thl_a_o);

        (eb_n => o0b) = (tlh_e_o, thl_e_o);
        (eb_n => o1b) = (tlh_e_o, thl_e_o);
        (eb_n => o2b) = (tlh_e_o, thl_e_o);
        (eb_n => o3b) = (tlh_e_o, thl_e_o);

        (oeb_n, pb => o0b) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oeb_n, pb => o1b) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oeb_n, pb => o2b) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oeb_n, pb => o3b) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
    endspecify

endmodule