// ============================================================================ // f538.v — 54F/74F538 1-of-8 Decoder (With 3-State Outputs) // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F538.txt (1980 Fairchild FAST Data Book, // pages 4-115 ... 4-117) — PRELIMINARY data sheet. // // One-of-eight decoder/demultiplexer with three active-HIGH address inputs // and eight mutually exclusive 3-state outputs. // - Polarity control P: P = L -> active-HIGH outputs (selected output // HIGH, others LOW); P = H -> active-LOW outputs (selected output LOW, // others HIGH). // - Enables: E1_n, E2_n active LOW and E3, E4 active HIGH. When not // enabled (any of E1_n, E2_n HIGH or E3, E4 LOW) all outputs equal the // P input. // - Either OE_n HIGH forces all outputs to the high-impedance state. // // Timing values from the data sheet AC Characteristics table // (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF). The preliminary sheet gives // TYP ONLY (min/max columns blank). // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f538 ( input wire a0, a1, a2, // address inputs (active HIGH) input wire e1_n, e2_n, // enable inputs (active LOW) input wire e3, e4, // enable inputs (active HIGH) input wire oe1_n, oe2_n, // output enables (active LOW) input wire p, // polarity control input output wire o0, o1, o2, o3, // 3-state outputs 0-3 output wire o4, o5, o6, o7 // 3-state outputs 4-7 ); wire en, oe_n; wire [7:0] dec; // Common enable: both active-LOW enables LOW and both active-HIGH // enables HIGH (per truth table disable rows). assign en = ~e1_n & ~e2_n & e3 & e4; // Either output enable HIGH forces the high-impedance state. assign oe_n = oe1_n | oe2_n; // One-hot decode, gated by the enable. Each output is the AND of all // three address bits against its own code (matching f138/f139's // construction) rather than a single indexed bit-select write: an // indexed write with an x-valued address index (`dec[addr] = 1'b1`) is // silently dropped by Verilog's bit-select semantics, which would read // as "disabled" instead of propagating the x. Written this way, an x on // an address bit only reaches the (at most two) outputs whose code // still matches the known bits. assign dec[0] = en & ~a2 & ~a1 & ~a0; assign dec[1] = en & ~a2 & ~a1 & a0; assign dec[2] = en & ~a2 & a1 & ~a0; assign dec[3] = en & ~a2 & a1 & a0; assign dec[4] = en & a2 & ~a1 & ~a0; assign dec[5] = en & a2 & ~a1 & a0; assign dec[6] = en & a2 & a1 & ~a0; assign dec[7] = en & a2 & a1 & a0; // Polarity control (XOR): selected output is ~P, all others P. assign o0 = oe_n ? 1'bz : (dec[0] ^ p); assign o1 = oe_n ? 1'bz : (dec[1] ^ p); assign o2 = oe_n ? 1'bz : (dec[2] ^ p); assign o3 = oe_n ? 1'bz : (dec[3] ^ p); assign o4 = oe_n ? 1'bz : (dec[4] ^ p); assign o5 = oe_n ? 1'bz : (dec[5] ^ p); assign o6 = oe_n ? 1'bz : (dec[6] ^ p); assign o7 = oe_n ? 1'bz : (dec[7] ^ p); specify // Propagation delay A_n to O_n (data sheet, TYP ONLY — preliminary // sheet, min/max blank: tPLH 12.5, tPHL 11.5 ns) specparam tlh_a_o = 12.5; specparam thl_a_o = 11.5; // Propagation delay E1_n or E2_n to O_n (data sheet, TYP ONLY: // tPLH 11.5, tPHL 11 ns) specparam tlh_e1_o = 11.5; specparam thl_e1_o = 11.0; // Propagation delay E3 or E4 to O_n (data sheet, TYP ONLY: // tPLH 14, tPHL 14.5 ns) specparam tlh_e3_o = 14.0; specparam thl_e3_o = 14.5; // Propagation delay P to O_n (data sheet, TYP ONLY: tPLH 13, // tPHL 12 ns) specparam tlh_p_o = 13.0; specparam thl_p_o = 12.0; // Output enable/disable time OE1_n or OE2_n to O_n (data sheet, // TYP ONLY: tPZH 5.0, tPZL 5.5, tPHZ 5.0, tPLZ 5.5 ns; disable // times measured with C_L = 5 pF) specparam tzh_oe_o = 5.0; specparam tzl_oe_o = 5.5; specparam thz_oe_o = 5.0; specparam tlz_oe_o = 5.5; (a0, a1, a2 => o0) = (tlh_a_o, thl_a_o); (a0, a1, a2 => o1) = (tlh_a_o, thl_a_o); (a0, a1, a2 => o2) = (tlh_a_o, thl_a_o); (a0, a1, a2 => o3) = (tlh_a_o, thl_a_o); (a0, a1, a2 => o4) = (tlh_a_o, thl_a_o); (a0, a1, a2 => o5) = (tlh_a_o, thl_a_o); (a0, a1, a2 => o6) = (tlh_a_o, thl_a_o); (a0, a1, a2 => o7) = (tlh_a_o, thl_a_o); (e1_n, e2_n => o0) = (tlh_e1_o, thl_e1_o); (e1_n, e2_n => o1) = (tlh_e1_o, thl_e1_o); (e1_n, e2_n => o2) = (tlh_e1_o, thl_e1_o); (e1_n, e2_n => o3) = (tlh_e1_o, thl_e1_o); (e1_n, e2_n => o4) = (tlh_e1_o, thl_e1_o); (e1_n, e2_n => o5) = (tlh_e1_o, thl_e1_o); (e1_n, e2_n => o6) = (tlh_e1_o, thl_e1_o); (e1_n, e2_n => o7) = (tlh_e1_o, thl_e1_o); (e3, e4 => o0) = (tlh_e3_o, thl_e3_o); (e3, e4 => o1) = (tlh_e3_o, thl_e3_o); (e3, e4 => o2) = (tlh_e3_o, thl_e3_o); (e3, e4 => o3) = (tlh_e3_o, thl_e3_o); (e3, e4 => o4) = (tlh_e3_o, thl_e3_o); (e3, e4 => o5) = (tlh_e3_o, thl_e3_o); (e3, e4 => o6) = (tlh_e3_o, thl_e3_o); (e3, e4 => o7) = (tlh_e3_o, thl_e3_o); // 6-delay form, IEEE order (0->1, 1->0, 0->Z, Z->1, 1->Z, Z->0): // P causes only 0->1/1->0 transitions, OE_n only Z transitions. (oe1_n, oe2_n, p => o0) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oe1_n, oe2_n, p => o1) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oe1_n, oe2_n, p => o2) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oe1_n, oe2_n, p => o3) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oe1_n, oe2_n, p => o4) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oe1_n, oe2_n, p => o5) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oe1_n, oe2_n, p => o6) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oe1_n, oe2_n, p => o7) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); endspecify endmodule