// ============================================================================
// f537.v — 54F/74F537 1-of-10 Decoder (With 3-State Outputs)
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F537.txt (1980 Fairchild FAST Data Book,
//         pages 4-112 ... 4-114) — PRELIMINARY data sheet.
//
// One-of-ten decoder/demultiplexer with four active-HIGH BCD address
// inputs and ten mutually exclusive 3-state outputs.
//   - Polarity control P: P = L -> active-HIGH outputs (selected output
//     HIGH, others LOW); P = H -> active-LOW outputs (selected output LOW,
//     others HIGH).
//   - Enables: E1_n active LOW and E2 active HIGH. When not enabled
//     (E1_n = H or E2 = L) all outputs equal the P input.
//   - Address codes greater than BCD nine (10..15) select nothing: all
//     outputs equal the P input.
//   - OE_n HIGH forces all outputs to the high-impedance state.
//
// (The logic-diagram description in the doc mentions an inverting output
// buffer, which would contradict the truth table; the truth table is
// authoritative and is what is modeled here.)
//
// Timing values from the data sheet AC Characteristics table
// (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF). The preliminary sheet gives
// TYP ONLY (min/max columns blank).
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f537 (
    input  wire a0, a1, a2, a3,         // address inputs (active HIGH)
    input  wire e1_n,                   // enable input (active LOW)
    input  wire e2,                     // enable input (active HIGH)
    input  wire oe_n,                   // output enable (active LOW)
    input  wire p,                      // polarity control input
    output wire o0, o1, o2, o3, o4,     // 3-state outputs 0-4
    output wire o5, o6, o7, o8, o9      // 3-state outputs 5-9
);

    wire       en;
    wire [9:0] dec;

    // Common enable: E1_n LOW and E2 HIGH (per truth table disable rows).
    assign en = ~e1_n & e2;

    // One-hot BCD decode, gated by the enable. Each output is the AND of
    // all four address bits against its own code (matching f138/f139's
    // construction) rather than a single indexed bit-select write: an
    // indexed write with an x-valued address index (`dec[addr] = 1'b1`) is
    // silently dropped by Verilog's bit-select semantics, which would read
    // as "disabled" instead of propagating the x. Written this way, an x on
    // an address bit only reaches the (at most two) outputs whose code
    // still matches the known bits; codes 10-15 match no product term, so
    // they need no separate exclusion.
    assign dec[0] = en & ~a3 & ~a2 & ~a1 & ~a0;
    assign dec[1] = en & ~a3 & ~a2 & ~a1 &  a0;
    assign dec[2] = en & ~a3 & ~a2 &  a1 & ~a0;
    assign dec[3] = en & ~a3 & ~a2 &  a1 &  a0;
    assign dec[4] = en & ~a3 &  a2 & ~a1 & ~a0;
    assign dec[5] = en & ~a3 &  a2 & ~a1 &  a0;
    assign dec[6] = en & ~a3 &  a2 &  a1 & ~a0;
    assign dec[7] = en & ~a3 &  a2 &  a1 &  a0;
    assign dec[8] = en &  a3 & ~a2 & ~a1 & ~a0;
    assign dec[9] = en &  a3 & ~a2 & ~a1 &  a0;

    // Polarity control (XOR): selected output is ~P, all others P.
    // OE_n HIGH forces the high-impedance state.
    assign o0 = oe_n ? 1'bz : (dec[0] ^ p);
    assign o1 = oe_n ? 1'bz : (dec[1] ^ p);
    assign o2 = oe_n ? 1'bz : (dec[2] ^ p);
    assign o3 = oe_n ? 1'bz : (dec[3] ^ p);
    assign o4 = oe_n ? 1'bz : (dec[4] ^ p);
    assign o5 = oe_n ? 1'bz : (dec[5] ^ p);
    assign o6 = oe_n ? 1'bz : (dec[6] ^ p);
    assign o7 = oe_n ? 1'bz : (dec[7] ^ p);
    assign o8 = oe_n ? 1'bz : (dec[8] ^ p);
    assign o9 = oe_n ? 1'bz : (dec[9] ^ p);

    specify
        // Propagation delay A_n to O_n (data sheet, TYP ONLY — preliminary
        // sheet, min/max blank: tPLH 12.5, tPHL 11.5 ns)
        specparam tlh_a_o  = 12.5;
        specparam thl_a_o  = 11.5;

        // Propagation delay E1_n to O_n (data sheet, TYP ONLY: tPLH 11.5,
        // tPHL 11 ns)
        specparam tlh_e1_o = 11.5;
        specparam thl_e1_o = 11.0;

        // Propagation delay E2 to O_n (data sheet, TYP ONLY: tPLH 14,
        // tPHL 14.5 ns)
        specparam tlh_e2_o = 14.0;
        specparam thl_e2_o = 14.5;

        // Propagation delay P to O_n (data sheet, TYP ONLY: tPLH 13,
        // tPHL 12 ns)
        specparam tlh_p_o  = 13.0;
        specparam thl_p_o  = 12.0;

        // Output enable/disable time OE_n to O_n (data sheet, TYP ONLY:
        // tPZH 5.0, tPZL 5.5, tPHZ 5.0, tPLZ 5.0 ns; disable times
        // measured with C_L = 5 pF)
        specparam tzh_oe_o = 5.0;
        specparam tzl_oe_o = 5.5;
        specparam thz_oe_o = 5.0;
        specparam tlz_oe_o = 5.0;

        (a0, a1, a2, a3 => o0) = (tlh_a_o, thl_a_o);
        (a0, a1, a2, a3 => o1) = (tlh_a_o, thl_a_o);
        (a0, a1, a2, a3 => o2) = (tlh_a_o, thl_a_o);
        (a0, a1, a2, a3 => o3) = (tlh_a_o, thl_a_o);
        (a0, a1, a2, a3 => o4) = (tlh_a_o, thl_a_o);
        (a0, a1, a2, a3 => o5) = (tlh_a_o, thl_a_o);
        (a0, a1, a2, a3 => o6) = (tlh_a_o, thl_a_o);
        (a0, a1, a2, a3 => o7) = (tlh_a_o, thl_a_o);
        (a0, a1, a2, a3 => o8) = (tlh_a_o, thl_a_o);
        (a0, a1, a2, a3 => o9) = (tlh_a_o, thl_a_o);

        (e1_n => o0) = (tlh_e1_o, thl_e1_o);
        (e1_n => o1) = (tlh_e1_o, thl_e1_o);
        (e1_n => o2) = (tlh_e1_o, thl_e1_o);
        (e1_n => o3) = (tlh_e1_o, thl_e1_o);
        (e1_n => o4) = (tlh_e1_o, thl_e1_o);
        (e1_n => o5) = (tlh_e1_o, thl_e1_o);
        (e1_n => o6) = (tlh_e1_o, thl_e1_o);
        (e1_n => o7) = (tlh_e1_o, thl_e1_o);
        (e1_n => o8) = (tlh_e1_o, thl_e1_o);
        (e1_n => o9) = (tlh_e1_o, thl_e1_o);

        (e2 => o0) = (tlh_e2_o, thl_e2_o);
        (e2 => o1) = (tlh_e2_o, thl_e2_o);
        (e2 => o2) = (tlh_e2_o, thl_e2_o);
        (e2 => o3) = (tlh_e2_o, thl_e2_o);
        (e2 => o4) = (tlh_e2_o, thl_e2_o);
        (e2 => o5) = (tlh_e2_o, thl_e2_o);
        (e2 => o6) = (tlh_e2_o, thl_e2_o);
        (e2 => o7) = (tlh_e2_o, thl_e2_o);
        (e2 => o8) = (tlh_e2_o, thl_e2_o);
        (e2 => o9) = (tlh_e2_o, thl_e2_o);

        // 6-delay form, IEEE order (0->1, 1->0, 0->Z, Z->1, 1->Z, Z->0):
        // P causes only 0->1/1->0 transitions, OE_n only Z transitions.
        (oe_n, p => o0) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oe_n, p => o1) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oe_n, p => o2) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oe_n, p => o3) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oe_n, p => o4) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oe_n, p => o5) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oe_n, p => o6) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oe_n, p => o7) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oe_n, p => o8) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oe_n, p => o9) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
    endspecify

endmodule