// ============================================================================
// f374.v — 54F/74F374 Octal D-Type Flip-Flop (With 3-State Outputs)
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F374.txt (1980 Fairchild FAST Data Book,
//         pages 4-103 ... 4-104)
//
// Eight edge-triggered D-type flip-flops with 3-state true outputs. The
// flip-flops store the state of their D inputs on the LOW-to-HIGH Clock
// (CP) transition. Output Enable (OE_n) LOW drives the outputs; OE_n HIGH
// forces the high-impedance state without affecting the flip-flops.
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), min:typ:max ns.
// The data sheet f_max row was printed with no values; not modeled.
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f374 (
    input  wire oe_n,                   // 3-state output enable (active LOW)
    input  wire cp,                     // clock pulse (active rising edge)
    input  wire d0, d1, d2, d3,         // data inputs 0-3
    input  wire d4, d5, d6, d7,         // data inputs 4-7
    output wire o0, o1, o2, o3,         // 3-state outputs 0-3
    output wire o4, o5, o6, o7          // 3-state outputs 4-7
);

    // Edge-triggered flip-flop bank: D stored on the rising CP edge.
    reg [7:0] q_int;

    always @(posedge cp) begin
        q_int <= {d7, d6, d5, d4, d3, d2, d1, d0};
    end

    // 3-state output buffers (OE_n HIGH -> high impedance)
    assign o0 = oe_n ? 1'bz : q_int[0];
    assign o1 = oe_n ? 1'bz : q_int[1];
    assign o2 = oe_n ? 1'bz : q_int[2];
    assign o3 = oe_n ? 1'bz : q_int[3];
    assign o4 = oe_n ? 1'bz : q_int[4];
    assign o5 = oe_n ? 1'bz : q_int[5];
    assign o6 = oe_n ? 1'bz : q_int[6];
    assign o7 = oe_n ? 1'bz : q_int[7];

    specify
        // Propagation delay CP to O_n (data sheet: tPLH 3.0/5.5/9.0,
        // tPHL 3.0/5.5/9.0 ns)
        specparam tlh_cp_o = 3.0:5.5:9.0;
        specparam thl_cp_o = 3.0:5.5:9.0;

        // Output enable/disable time OE_n to O_n (data sheet:
        // tPZH 3.0/6.5/10, tPZL 3.0/6.5/10, tPHZ 3.0/5.5/8.0,
        // tPLZ 3.0/4.5/7.0 ns; disable times measured with C_L = 5 pF)
        specparam tzh_oe_o = 3.0:6.5:10;
        specparam tzl_oe_o = 3.0:6.5:10;
        specparam thz_oe_o = 3.0:5.5:8.0;
        specparam tlz_oe_o = 3.0:4.5:7.0;

        // 6-delay form, IEEE order (0->1, 1->0, 0->Z, Z->1, 1->Z, Z->0):
        // CP causes only 0->1/1->0 transitions, OE_n only Z transitions.
        (oe_n, cp => o0) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oe_n, cp => o1) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oe_n, cp => o2) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oe_n, cp => o3) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oe_n, cp => o4) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oe_n, cp => o5) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oe_n, cp => o6) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oe_n, cp => o7) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);

        // AC operating requirements (data sheet, +25 C 5.0 V minima):
        // ts(H) 2.0, ts(L) 2.0, th(H) 2.0, th(L) 2.0, tw(H) CP 7.0,
        // tw(L) CP 6.0 ns. Icarus Verilog does not support timing checks;
        // kept (guarded) for simulators that do.
`ifndef __ICARUS__
        specparam ts_h = 2.0;
        specparam ts_l = 2.0;
        specparam th_h = 2.0;
        specparam th_l = 2.0;
        specparam tw_cp_h = 7.0;
        specparam tw_cp_l = 6.0;

        $setup(d0, posedge cp, ts_h);
        $setup(d1, posedge cp, ts_h);
        $setup(d2, posedge cp, ts_h);
        $setup(d3, posedge cp, ts_h);
        $setup(d4, posedge cp, ts_h);
        $setup(d5, posedge cp, ts_h);
        $setup(d6, posedge cp, ts_h);
        $setup(d7, posedge cp, ts_h);
        $hold(posedge cp, d0, th_h);
        $hold(posedge cp, d1, th_h);
        $hold(posedge cp, d2, th_h);
        $hold(posedge cp, d3, th_h);
        $hold(posedge cp, d4, th_h);
        $hold(posedge cp, d5, th_h);
        $hold(posedge cp, d6, th_h);
        $hold(posedge cp, d7, th_h);
        $width(posedge cp, tw_cp_h);
        $width(negedge cp, tw_cp_l);
`endif
    endspecify

endmodule