// ============================================================================
// f257.v — 54F/74F257 Quad 2-Input Multiplexer (With 3-State Outputs)
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F257.txt (1980 Fairchild FAST Data Book,
//         pages 4-79 ... 4-81)
//
// Four 2-input multiplexers with a Common Data Select input S and a common
// active-LOW 3-state Output Enable (OE_n). When S is LOW the I0x inputs
// are selected, when HIGH the I1x inputs. Data appears at the outputs in
// true (non-inverted) form. A HIGH on OE_n forces all outputs to the high
// impedance state.
//
//   Zx = OE_n ? HiZ : (S ? I1x : I0x)
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), min:typ:max ns.
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f257 (
    input  wire s,          // common data select input
    input  wire oe_n,       // 3-state output enable (active LOW)
    input  wire i0a, i1a,   // source 0/1 data inputs, bit a
    output wire za,         // output a
    input  wire i0b, i1b,   // source 0/1 data inputs, bit b
    output wire zb,         // output b
    input  wire i0c, i1c,   // source 0/1 data inputs, bit c
    output wire zc,         // output c
    input  wire i0d, i1d,   // source 0/1 data inputs, bit d
    output wire zd          // output d
);

    assign za = oe_n ? 1'bz : (s ? i1a : i0a);
    assign zb = oe_n ? 1'bz : (s ? i1b : i0b);
    assign zc = oe_n ? 1'bz : (s ? i1c : i0c);
    assign zd = oe_n ? 1'bz : (s ? i1d : i0d);

    specify
        // Propagation delay In to Zn (data sheet: tPLH 2.0/4.0/6.0,
        // tPHL 2.0/3.5/4.5 ns)
        specparam tlh_i = 2.0:4.0:6.0;
        specparam thl_i = 2.0:3.5:4.5;

        // Propagation delay S to Zn (data sheet: tPLH 4.0/10/13,
        // tPHL 3.0/7.5/9.0 ns)
        specparam tlh_s = 4.0:10.0:13.0;
        specparam thl_s = 3.0:7.5:9.0;

        // Output enable time OE_n to Zn (data sheet: tPZH 2.0/5.0/7.0,
        // tPZL 2.0/5.5/7.0 ns)
        specparam tzh = 2.0:5.0:7.0;
        specparam tzl = 2.0:5.5:7.0;

        // Output disable time OE_n to Zn, C_L = 5 pF (data sheet:
        // tPHZ 2.0/4.0/6.0, tPLZ 2.0/4.0/6.0 ns)
        specparam thz = 2.0:4.0:6.0;
        specparam tlz = 2.0:4.0:6.0;

        // 6-delay form, IEEE order (0->1, 1->0, 0->Z, Z->1, 1->Z, Z->0)
        (oe_n, i0a, i1a => za) = (tlh_i, thl_i, tlz, tzh, thz, tzl);
        (oe_n, i0b, i1b => zb) = (tlh_i, thl_i, tlz, tzh, thz, tzl);
        (oe_n, i0c, i1c => zc) = (tlh_i, thl_i, tlz, tzh, thz, tzl);
        (oe_n, i0d, i1d => zd) = (tlh_i, thl_i, tlz, tzh, thz, tzl);
        (s => za) = (tlh_s, thl_s);
        (s => zb) = (tlh_s, thl_s);
        (s => zc) = (tlh_s, thl_s);
        (s => zd) = (tlh_s, thl_s);
    endspecify

endmodule