// ============================================================================
// f20.v — 54F/74F20 Dual 4-Input NAND Gate
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F20.txt (1980 Fairchild FAST Data Book, page 4-9)
//         (data sheet page marked "Preliminary")
//
// Logic function (each gate): Z = ~(A & B & C & D)
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), min:typ:max ns.
// The sheet's second row, C_L = 50 pF, gives min/max only:
//   A, B, C or D to Z   tPLH 2.0 / 6.0   tPHL 2.0 / 5.5 ns
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f20 (
    input  wire a1, b1, c1, d1, // gate 1 inputs
    output wire z1,             // gate 1 output
    input  wire a2, b2, c2, d2, // gate 2 inputs
    output wire z2              // gate 2 output
);

    assign z1 = ~(a1 & b1 & c1 & d1);
    assign z2 = ~(a2 & b2 & c2 & d2);

    specify
        // Propagation delay, A, B, C or D to Z (data sheet: tPLH 1.5/2.9/3.9,
        // tPHL 1.5/2.8/3.8 ns)
        specparam tlh = 1.5:2.9:3.9;
        specparam thl = 1.5:2.8:3.8;

        (a1, b1, c1, d1 => z1) = (tlh, thl);
        (a2, b2, c2, d2 => z2) = (tlh, thl);
    endspecify

endmodule