// ============================================================================
// f151.v — 54F/74F151 8-Input Multiplexer
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F151.txt (1980 Fairchild FAST Data Book,
//         pages 4-16 ... 4-18) — PRELIMINARY data sheet
//
// Selects one of eight data inputs under control of the Select inputs
// S0, S1, S2. Both assertion (Z) and negation (Z_n) outputs are provided.
// The Enable input (e_n) is active LOW: when HIGH, Z is forced LOW and
// Z_n is forced HIGH regardless of all other inputs.
//
//   Z   = ~e_n & (selected I_n)
//   Z_n =  e_n | ~(selected I_n)
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF). The sheet is
// preliminary: only TYPICAL values are given (min/max columns blank), so
// every specparam carries the typ value only.
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f151 (
    input  wire i0, i1, i2, i3,   // data inputs 0-3
    input  wire i4, i5, i6, i7,   // data inputs 4-7
    input  wire s0, s1, s2,       // select inputs
    input  wire e_n,              // enable input (active LOW)
    output wire z,                // data output
    output wire z_n               // inverted data output
);

    // Selected data input (internal node)
    wire d = s2 ? (s1 ? (s0 ? i7 : i6) : (s0 ? i5 : i4))
                : (s1 ? (s0 ? i3 : i2) : (s0 ? i1 : i0));

    assign z   = ~e_n & d;
    assign z_n =  e_n | ~d;

    specify
        // All values TYP only (preliminary data sheet; min/max columns
        // left blank), 54F/74F +25 C 5.0 V C_L = 15 pF.

        // Propagation delay S_n to Z_n (data sheet: typ 6.3 / 6.2 ns)
        specparam tlh_s_zn = 6.3;
        specparam thl_s_zn = 6.2;

        // Propagation delay S_n to Z (data sheet: typ 8.1 / 7.9 ns)
        specparam tlh_s_z = 8.1;
        specparam thl_s_z = 7.9;

        // Propagation delay E_n to Z_n (data sheet: typ 4.6 / 4.5 ns)
        specparam tlh_e_zn = 4.6;
        specparam thl_e_zn = 4.5;

        // Propagation delay E_n to Z (data sheet: typ 6.4 / 6.2 ns)
        specparam tlh_e_z = 6.4;
        specparam thl_e_z = 6.2;

        // Propagation delay I_n to Z_n (data sheet: typ 2.9 / 2.8 ns)
        specparam tlh_i_zn = 2.9;
        specparam thl_i_zn = 2.8;

        // Propagation delay I_n to Z (data sheet: typ 4.7 / 4.5 ns)
        specparam tlh_i_z = 4.7;
        specparam thl_i_z = 4.5;

        (s0, s1, s2 => z)   = (tlh_s_z,  thl_s_z);
        (s0, s1, s2 => z_n) = (tlh_s_zn, thl_s_zn);
        (e_n => z)          = (tlh_e_z,  thl_e_z);
        (e_n => z_n)        = (tlh_e_zn, thl_e_zn);
        (i0, i1, i2, i3, i4, i5, i6, i7 => z)   = (tlh_i_z,  thl_i_z);
        (i0, i1, i2, i3, i4, i5, i6, i7 => z_n) = (tlh_i_zn, thl_i_zn);
    endspecify

endmodule