// ============================================================================
// f139.v — 54F/74F139 Dual 1-of-4 Decoder/Demultiplexer
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F139.txt (1985 Fairchild FAST Data Book,
//         pages 4-49 ... 4-52 — the 1980 data book carries the 'F139 in
//         its Section 3 selection guide only, page 3-15).
//
// Two completely independent 1-of-4 decoders, each accepting two binary
// weighted address inputs (A0, A1) and providing four mutually exclusive
// active LOW outputs (/O0 - /O3). Each decoder has its own active LOW
// Enable (/E); when /E is HIGH all four of that decoder's outputs are
// forced HIGH. The Enable can be used as the data input of a 4-output
// demultiplexer. Each half generates all four minterms of two variables.
//
//   /On = ~(~/E & ({a1, a0} == n))
//
// The "a" and "b" suffixes distinguish the two decoders; they share only
// V_CC and GND.
//
// Timing values from the data sheet AC Characteristics table, T_A = +25 C,
// V_CC = +5.0 V, C_L = 50 pF column, min:typ:max ns. The sheet's second
// column, 74F over the commercial T_A/V_CC range, gives min/max only:
//
//   A0 or A1 to /On   tPLH 3.0 / 8.5   tPHL 4.0 / 9.0 ns
//   /E to /On         tPLH 3.5 / 8.0   tPHL 3.0 / 7.5 ns
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f139 (
    input  wire e_na,                           // half a enable (active LOW)
    input  wire a0a, a1a,                       // half a address inputs
    output wire o0a_n, o1a_n, o2a_n, o3a_n,     // half a outputs (active LOW)
    input  wire e_nb,                           // half b enable (active LOW)
    input  wire a0b, a1b,                       // half b address inputs
    output wire o0b_n, o1b_n, o2b_n, o3b_n      // half b outputs (active LOW)
);

    // Internal enable terms: each half's outputs are all HIGH unless that
    // half's /E is LOW.
    wire ea = ~e_na;
    wire eb = ~e_nb;

    assign o0a_n = ~(ea & ~a1a & ~a0a);
    assign o1a_n = ~(ea & ~a1a &  a0a);
    assign o2a_n = ~(ea &  a1a & ~a0a);
    assign o3a_n = ~(ea &  a1a &  a0a);

    assign o0b_n = ~(eb & ~a1b & ~a0b);
    assign o1b_n = ~(eb & ~a1b &  a0b);
    assign o2b_n = ~(eb &  a1b & ~a0b);
    assign o3b_n = ~(eb &  a1b &  a0b);

    specify
        // T_A = +25 C, V_CC = +5.0 V, C_L = 50 pF, min:typ:max ns.

        // Propagation delay A0 or A1 to /On
        // (data sheet: tPLH 3.5/5.3/7.5, tPHL 4.0/6.1/8.0)
        specparam tlh_a = 3.5:5.3:7.5;
        specparam thl_a = 4.0:6.1:8.0;

        // Propagation delay /E to /On
        // (data sheet: tPLH 3.5/5.4/7.0, tPHL 3.0/4.7/6.5)
        specparam tlh_e = 3.5:5.4:7.0;
        specparam thl_e = 3.0:4.7:6.5;

        (a0a, a1a => o0a_n) = (tlh_a, thl_a);
        (a0a, a1a => o1a_n) = (tlh_a, thl_a);
        (a0a, a1a => o2a_n) = (tlh_a, thl_a);
        (a0a, a1a => o3a_n) = (tlh_a, thl_a);

        (e_na => o0a_n) = (tlh_e, thl_e);
        (e_na => o1a_n) = (tlh_e, thl_e);
        (e_na => o2a_n) = (tlh_e, thl_e);
        (e_na => o3a_n) = (tlh_e, thl_e);

        (a0b, a1b => o0b_n) = (tlh_a, thl_a);
        (a0b, a1b => o1b_n) = (tlh_a, thl_a);
        (a0b, a1b => o2b_n) = (tlh_a, thl_a);
        (a0b, a1b => o3b_n) = (tlh_a, thl_a);

        (e_nb => o0b_n) = (tlh_e, thl_e);
        (e_nb => o1b_n) = (tlh_e, thl_e);
        (e_nb => o2b_n) = (tlh_e, thl_e);
        (e_nb => o3b_n) = (tlh_e, thl_e);
    endspecify

endmodule