// ============================================================================
// f10.v — 54F/74F10 Triple 3-Input NAND Gate
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F10.txt (1980 Fairchild FAST Data Book, page 4-7)
//
// Logic function (each gate): Z = ~(A & B & C)
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), min:typ:max ns.
// The sheet's second row, C_L = 50 pF, gives min/max only:
//   A, B or C to Z   tPLH 2.0 / 6.0   tPHL 2.0 / 5.5 ns
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f10 (
    input  wire a1, b1, c1, // gate 1 inputs
    output wire z1,         // gate 1 output
    input  wire a2, b2, c2, // gate 2 inputs
    output wire z2,         // gate 2 output
    input  wire a3, b3, c3, // gate 3 inputs
    output wire z3          // gate 3 output
);

    assign z1 = ~(a1 & b1 & c1);
    assign z2 = ~(a2 & b2 & c2);
    assign z3 = ~(a3 & b3 & c3);

    specify
        // Propagation delay, A, B or C to Z (data sheet: tPLH 1.5/2.9/3.9,
        // tPHL 1.5/2.7/3.7 ns)
        specparam tlh = 1.5:2.9:3.9;
        specparam thl = 1.5:2.7:3.7;

        (a1, b1, c1 => z1) = (tlh, thl);
        (a2, b2, c2 => z2) = (tlh, thl);
        (a3, b3, c3 => z3) = (tlh, thl);
    endspecify

endmodule