======================================================================== 74F524 8-BIT REGISTERED COMPARATOR ======================================================================== Family: Fairchild FAST (Advanced Schottky TTL) Source: 1985 Fairchild FAST Data Book, pages 4-378 ... 4-385. The 1980 data book carries the 'F524 in its Section 3 selection guide only (page 3-35, description and logic symbol). Status: Released data sheet Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C DESCRIPTION ----------- The 'F524 is an 8-bit bidirectional register with parallel input and output plus serial input and output progressing from LSB to MSB. All data inputs, serial and parallel, are loaded by the rising edge of the input clock. The device functions are controlled by two control lines (S0, S1) to execute shift, load, hold and read out. An 8-bit comparator examines the data stored in the registers and on the data bus. Three true-HIGH, open-collector outputs representing 'register equal to bus', 'register greater than bus' and 'register less than bus' are provided. These outputs can be disabled to the OFF state by the use of Status Enable (/SE). A mode control has also been provided to allow twos complement as well as magnitude compare. Linking inputs are provided for expansion to longer words. o 8-Bit Bidirectional Register with Bus-Oriented Input-Output o Independent Serial Input-Output to Register o Register Bus Comparator with 'Equal to', 'Greater then' and 'Less than' Outputs o Cascadable in Groups of Eight Bits o Open-Collector Comparator Outputs for AND-Wired Expansion o Twos Complement or Magnitude Compare FUNCTIONAL DESCRIPTION ---------------------- The 'F524 contains eight D-type flip-flops connected as a shift register with provision for either parallel or serial loading. Parallel data may be read from or loaded into the registers via the data bus I/O0-I/O7. Serial data is entered from the C/SI input and may be shifted into the register and out through the C/SO output. Both parallel and serial data entry occur on the rising edge of the input clock (CP). The operation of the shift register is controlled by two signals S0 and S1 according to the Select Truth Table. The 3-state parallel output buffers are enabled only in the Read mode. One port of an 8-bit comparator is attached to the data bus while the other port is tied to the outputs of the internal register. Three active-OFF, open-collector outputs indicate whether the contents held in the shift register are 'greater than', (GT), 'less than' (LT), or 'equal to' (EQ) the data on the input bus. A HIGH signal on the Status Enable (/SE) input disables these outputs to the OFF state. A mode control input (M) allows selection between a straightforward magnitude compare or a comparison between twos complement numbers. For 'greater than' or 'less than' detection, the C/SI input must be held HIGH, as indicated in the Status Truth Table. The internal logic is arranged such that a LOW signal on the C/SI input disables the 'greater than' and 'less than' outputs. The C/SO output will be forced HIGH if the 'equal to' status condition exists, otherwise C/SO will be held LOW. These facilities enable the 'F524 to be cascaded for word length greater than eight bits. Word length expansion (in groups of eight bits) can be achieved by connecting the C/SO output of the more significant byte to the C/SI input of the next less significant byte and also to its own /SE input (see Figure a). The C/SI input of the most significant device is held HIGH while the /SE input of the least significant device is held LOW. The corresponding status outputs are AND-wired together. In the case of twos complement number compare, only the Mode input to the most significant device should be HIGH. The Mode inputs to all other cascaded devices are held LOW. Suppose that an inequality condition is detected in the most significant device. Assuming that the byte stored in the register is greater than the byte on the data bus, the EQ and LT outputs will be pulled LOW and the GT output will float HIGH. Also the C/SO output of the most significant device will be forced LOW, disabling the subsequent devices but enabling its own status outputs. The correct status condition is thus indicated. The same applies if the registered byte is less than the data byte, only in this case the EQ and GT outputs go LOW and LT output floats HIGH. If an equality condition is detected in the most significant device, its C/SO output is forced HIGH. This enables the next less significant device and also disables its own status outputs. In this way, the status output priority is handed down to the next less significant device which now effectively becomes the most significant byte. The worst case propagation delay for a compare operation involving 'n' cascaded 'F524s will be when an equality condition is detected in all but the least significant byte. In this case, the status priority has to ripple all the way down the chain before the correct status output is established. Typically, this will take 35 + 6(n-2) ns. CONNECTION DIAGRAM (20-pin DIP) ------------------------------- Pin Function Pin Function --- --------------------------- --- --------------------------- 1 S0 Mode Select 0 20 Vcc 2 I/O0 Parallel I/O bit 0 19 S1 Mode Select 1 3 I/O1 Parallel I/O bit 1 18 /SE Status Enable 4 I/O2 Parallel I/O bit 2 17 C/SI Status/Serial input 5 I/O3 Parallel I/O bit 3 16 C/SO Status/Serial output 6 I/O4 Parallel I/O bit 4 15 EQ Register = bus 7 I/O5 Parallel I/O bit 5 14 GT Register > bus 8 I/O6 Parallel I/O bit 6 13 LT Register < bus 9 I/O7 Parallel I/O bit 7 12 M Compare Mode Select 10 GND 11 CP Clock Pulse EQ, GT and LT are open-collector outputs, so the corresponding pins of cascaded packages can be tied together to AND-wire the status. SELECT TRUTH TABLE ------------------ S0 S1 Operation -- -- --------------------------------------------- L L Hold -- Retains data in shift register L H Read -- Read contents in register onto data bus H L Shift -- Allows serial shifting on next rising clock edge H H Load -- Load data on bus into register NUMBER REPRESENTATION SELECT TABLE ---------------------------------- M Operation -- ---------------------- L Magnitude compare H Twos complement compare STATUS TRUTH TABLE (Hold Mode) ------------------------------ Inputs Outputs --------------------------------- --------------------- /SE C/SI Data Comparison EQ GT LT C/SO --- ---- ---------------------- --- --- --- ---- H X X H H H 1 L L OA-OH > I/O0-I/O7 L H H L L L OA-OH = I/O0-I/O7 H H H L L L OA-OH < I/O0-I/O7 L H H L L H OA-OH > I/O0-I/O7 L H L L L H OA-OH = I/O0-I/O7 H L L H L H OA-OH < I/O0-I/O7 L L H L 1 = HIGH if data are equal, otherwise LOW. H = HIGH voltage level; L = LOW voltage level; X = immaterial. INPUT LOADING / FAN-OUT ----------------------- Pin Names Description U.L. HIGH/LOW ------------ -------------------------------------- ------------- S0, S1 Mode Select Inputs 0.5 / 0.375 C/SI Status Priority or Serial Data Input 0.5 / 0.375 CP Clock Pulse Input (Active Rising Edge) 0.5 / 0.375 /SE Status Enable Input (Active LOW) 0.5 / 0.375 M Compare Mode Select Input 0.5 / 0.375 I/O0 - I/O7 Parallel Data Inputs or 1.75 / 0.406 3-State Parallel Data Outputs 75 / 15 C/SO Status Priority or Serial Data Output 25 / 12.5 LT Register Less Than Bus Output OC* / 12.5 EQ Register Equal Bus Output OC* / 12.5 GT Register Greater Than Bus Output OC* / 12.5 *OC = Open Collector DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE --------------------------------------------------- Symbol Parameter Min Typ Max Units Conditions ------ -------------------- --- --- --- ----- ------------------------- ICC Power Supply Current 128 180 mA S0, S1, /SE, C/SI = HIGH CP, I/O0-I/O7, Register = LOW AC CHARACTERISTICS ------------------ TA = +25 C 74F Vcc = +5.0V TA/Vcc = Com Symbol Parameter CL Min Typ Max Min Max Units ------ ----------------------------- ----- ---- ---- ---- ---- ---- ----- fmax Maximum Shift Frequency -- 50.0 75.0 -- 50 -- MHz tPLH Prop Delay I/On to EQ 50 pF 9.0 16.5 20.0 9.0 21.0 ns tPHL Prop Delay I/On to EQ 50 pF 5.0 9.5 12.0 5.0 13.0 ns tPLH Prop Delay I/On to GT 50 pF 8.5 14.1 19.0 8.5 20.0 ns tPHL Prop Delay I/On to GT 50 pF 6.5 13.0 16.5 6.5 17.5 ns tPLH Prop Delay I/On to LT 50 pF 7.0 15.5 20.0 7.0 21.0 ns tPHL Prop Delay I/On to LT 50 pF 4.5 10.0 14.0 4.5 15.0 ns tPLH Prop Delay I/On to C/SO 50 pF 8.0 15.2 19.5 8.0 20.5 ns tPHL Prop Delay I/On to C/SO 50 pF 6.0 12.5 16.0 6.0 17.0 ns tPLH Prop Delay CP to EQ 50 pF 10.0 20.0 25.0 10.0 26.0 ns tPHL Prop Delay CP to EQ 50 pF 4.0 8.5 16.5 4.0 17.5 ns tPLH Prop Delay CP to GT 50 pF 10.0 16.5 21.0 10.0 22.0 ns tPHL Prop Delay CP to GT 50 pF 8.5 17.0 22.0 8.5 23.0 ns tPLH Prop Delay CP to LT 50 pF 9.0 20.0 25.0 9.0 26.0 ns tPHL Prop Delay CP to LT 50 pF 5.5 13.5 17.0 5.5 18.0 ns tPLH Prop Delay CP to C/SO 50 pF 8.5 16.5 21.0 8.5 22.0 ns (Compare) tPLH Prop Delay CP to C/SO 50 pF 5.0 10.0 13.0 5.0 14.0 ns (Serial Shift) tPHL Prop Delay CP to C/SO 50 pF 4.5 9.0 11.5 4.5 12.5 ns (Serial Shift) tPLH Prop Delay C/SI to GT 50 pF 9.0 15.0 19.0 9.0 20.0 ns tPHL Prop Delay C/SI to GT 50 pF 3.0 6.5 8.5 3.0 9.5 ns tPLH Prop Delay C/SI to LT 50 pF 8.0 15.5 20.0 8.0 21.0 ns tPHL Prop Delay C/SI to LT 50 pF 3.5 6.5 8.5 3.5 9.5 ns tPLH Prop Delay S0, S1 to EQ 50 pF 15.0 25.0 33.0 15.0 35.0 ns tPHL Prop Delay S0, S1 to EQ 50 pF 9.0 15.0 19.0 9.0 20.0 ns tPLH Prop Delay S0, S1 to GT 50 pF 10.5 18.0 23.0 10.5 24.0 ns tPHL Prop Delay S0, S1 to GT 50 pF 10.5 18.0 23.0 10.5 24.0 ns tPLH Prop Delay S0, S1 to LT 50 pF 13.0 22.0 28.0 13.0 30.0 ns tPHL Prop Delay S0, S1 to LT 50 pF 12.0 19.0 24.0 12.0 25.0 ns tPLH Prop Delay S0, S1 to C/SO 50 pF 6.5 11.5 14.5 6.5 15.5 ns tPHL Prop Delay S0, S1 to C/SO 50 pF 5.5 14.0 18.0 5.5 19.0 ns tPLH Prop Delay /SE to EQ 50 pF 3.5 8.0 10.5 3.5 11.5 ns tPHL Prop Delay /SE to EQ 50 pF 2.5 6.0 8.0 2.5 9.0 ns tPLH Prop Delay /SE to GT 50 pF 6.5 12.5 16.0 6.5 17.0 ns tPHL Prop Delay /SE to GT 50 pF 3.5 6.5 8.0 3.5 9.0 ns tPLH Prop Delay /SE to LT 50 pF 5.0 10.5 13.5 5.0 14.5 ns tPHL Prop Delay /SE to LT 50 pF 3.5 6.0 8.0 3.5 9.0 ns tPLH Prop Delay C/SI to C/SO 50 pF 4.0 8.5 11.0 4.0 12.0 ns tPHL Prop Delay C/SI to C/SO 50 pF 4.0 8.5 11.0 4.0 12.0 ns tPLH Prop Delay M to GT 50 pF 8.0 15.0 19.5 8.0 20.5 ns tPHL Prop Delay M to GT 50 pF 6.0 12.0 15.5 6.0 16.5 ns tPLH Prop Delay M to LT 50 pF 8.0 17.0 22.0 8.0 23.0 ns tPHL Prop Delay M to LT 50 pF 5.5 9.5 12.0 4.5 13.0 ns tPZH Output Enable Time S0, S1 to 50 pF 4.5 10.0 13.0 4.5 14.0 ns I/On tPZL Output Enable Time S0, S1 to 50 pF 5.5 11.0 15.0 5.5 16.0 ns I/On tPHZ Output Disable Time S0, S1 to 50 pF 3.5 8.0 12.0 3.5 13.0 ns I/On tPLZ Output Disable Time S0, S1 to 50 pF 4.5 9.6 12.5 4.5 13.5 ns I/On AC OPERATING REQUIREMENTS ------------------------- TA = +25 C 74F Vcc = +5.0V TA/Vcc = Com Symbol Parameter Min Typ Max Min Max Units ------ ----------------------------------- ---- --- --- ---- --- ----- ts (H) Setup Time, HIGH -- I/On to CP 6.0 -- -- 6.0 -- ns ts (L) Setup Time, LOW -- I/On to CP 6.0 -- -- 6.0 -- ns th (H) Hold Time, HIGH -- I/On to CP 0 -- -- 0 -- ns th (L) Hold Time, LOW -- I/On to CP 0 -- -- 0 -- ns ts (H) Setup Time, HIGH -- S0 or S1 to CP 10.0 -- -- 10.0 -- ns ts (L) Setup Time, LOW -- S0 or S1 to CP 10.0 -- -- 10.0 -- ns th (H) Hold Time, HIGH -- S0 or S1 to CP 0 -- -- 0 -- ns th (L) Hold Time, LOW -- S0 or S1 to CP 0 -- -- 0 -- ns ts (H) Setup Time, HIGH -- C/SI to CP 7.0 -- -- 7.0 -- ns ts (L) Setup Time, LOW -- C/SI to CP 7.0 -- -- 7.0 -- ns th (H) Hold Time, HIGH -- C/SI to CP 0 -- -- 0 -- ns th (L) Hold Time, LOW -- C/SI to CP 0 -- -- 0 -- ns tw (H) Clock Pulse Width, HIGH 5.0 -- -- 5.0 -- ns