======================================================================== 74F374 OCTAL D-TYPE FLIP-FLOP (WITH 3-STATE OUTPUTS) ======================================================================== Family: Fairchild FAST (Advanced Schottky TTL) Source: 1980 Fairchild FAST Data Book, pages 4-103 ... 4-104 Status: Released data sheet Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C DESCRIPTION ----------- The 'F374 is a high speed, low power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (/OE) are common to all flip-flops. o EDGE-TRIGGERED D-TYPE INPUTS o BUFFERED POSITIVE EDGE-TRIGGERED CLOCK o 3-STATE OUTPUTS FOR BUS ORIENTED APPLICATIONS FUNCTIONAL DESCRIPTION ---------------------- The 'F374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-state true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (/OE) LOW, the contents of the eight flip-flops are available at the outputs. When /OE is HIGH, the outputs go to the high impedance state. Operation of the /OE input does not affect the state of the flip-flops. CONNECTION DIAGRAM (20-pin DIP) ------------------------------- Pin Function Pin Function --- -------------------------- --- ------------------------------------- 1 /OE 3-State Output Enable 20 Vcc (active LOW) 2 O0 Output 0 19 O7 Output 7 3 D0 Data input 0 18 D7 Data input 7 4 D1 Data input 1 17 D6 Data input 6 5 O1 Output 1 16 O6 Output 6 6 O2 Output 2 15 O5 Output 5 7 D2 Data input 2 14 D5 Data input 5 8 D3 Data input 3 13 D4 Data input 4 9 O3 Output 3 12 O4 Output 4 10 GND 11 CP Clock Pulse (active rising edge) TRUTH TABLE ----------- Dn CP /OE On --- --- --- --- H ^ L H L ^ L L X X H Z H = HIGH voltage level; L = LOW voltage level; X = immaterial; Z = high impedance; ^ = LOW-to-HIGH clock transition. INPUT LOADING / FAN-OUT ----------------------- Pin Names Description U.L. HIGH/LOW --------- ---------------------------------------- ------------- D0 - D7 Data Inputs 0.5 / 0.375 CP Clock Pulse Input (Active Rising Edge) 0.5 / 0.375 /OE 3-State Output Enable Input (Active LOW) 0.5 / 0.375 O0 - O7 3-State Outputs 25 / 12.5 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE --------------------------------------------------- Conditions for all rows: Vcc = Max, Dn = Gnd, /OE = 4.5 V. Symbol Parameter Min Typ Max Units ------ -------------------------------------- --- --- --- ----- ICC Power Supply Current (All Outputs OFF) 55 86 mA AC CHARACTERISTICS ------------------ Symbol Parameter Min Typ Max Units ------ -------------------------- --- --- --- ----- fmax Maximum Clock Frequency -- -- -- MHz tPLH Propagation Delay CP to On 3.0 5.5 9.0 ns tPHL Propagation Delay CP to On 3.0 5.5 9.0 ns tPZH Output Enable Time 3.0 6.5 10 ns tPZL Output Enable Time 3.0 6.5 10 ns tPHZ Output Disable Time (1) 3.0 5.5 8.0 ns tPLZ Output Disable Time (1) 3.0 4.5 7.0 ns (1) Disable times measured with CL = 5 pF. AC OPERATING REQUIREMENTS ------------------------- Symbol Parameter Min Typ Max Units ------ ---------------------------- --- --- --- ----- ts (H) Setup Time, HIGH -- Dn to CP 2.0 -- -- ns ts (L) Setup Time, LOW -- Dn to CP 2.0 -- -- ns th (H) Hold Time, HIGH -- Dn to CP 2.0 -- -- ns th (L) Hold Time, LOW -- Dn to CP 2.0 -- -- ns tw (H) CP Pulse Width, HIGH 7.0 -- -- ns tw (L) CP Pulse Width, LOW 6.0 -- -- ns