======================================================================== 74F353 DUAL 4-INPUT MULTIPLEXER, INVERTING (WITH 3-STATE OUTPUTS) ======================================================================== Family: Fairchild FAST (Advanced Schottky TTL) Source: 1980 Fairchild FAST Data Book, pages 4-97 ... 4-99 Status: PRELIMINARY -- page 4-97 carries a "Preliminary" watermark. Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C DESCRIPTION ----------- The 'F353 is a dual 4-input multiplexer with 3-state outputs. It can select two bits of data from four sources using common select inputs. The outputs may be individually switched to a high impedance state with a HIGH on the respective Output Enable (/OE) inputs, allowing the outputs to interface directly with bus oriented systems. o INVERTED VERSION OF 'F253 o MULTIFUNCTION CAPABILITY o SEPARATE ENABLES FOR EACH MULTIPLEXER FUNCTIONAL DESCRIPTION ---------------------- The 'F353 contains two identical 4-input multiplexers with 3-state outputs. They select two bits from four sources selected by common Select inputs (S0, S1). The 4-input multiplexers have individual Output Enable (/OEa, /OEb) inputs which, when HIGH, force the outputs to a high impedance (high Z) state. The logic equations for the outputs are shown below: /Za = NOT[ /OEa * ( I0a*/S1*/S0 + I1a*/S1*S0 + I2a*S1*/S0 + I3a*S1*S0 ) ] /Zb = NOT[ /OEb * ( I0b*/S1*/S0 + I1b*/S1*S0 + I2b*S1*/S0 + I3b*S1*S0 ) ] If the outputs of 3-state devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to 3-state devices whose outputs are tied together are designed so that there is no overlap. CONNECTION DIAGRAM (16-pin DIP) ------------------------------- The pin functions on this part are too long for the usual two-up layout, so all 16 pins are listed in one column. Pin Function --- --------------------------------------- 1 /OEa Side A Output Enable (active LOW) 2 S1 Common Select 1 3 I3a Side A data input 3 4 I2a Side A data input 2 5 I1a Side A data input 1 6 I0a Side A data input 0 7 /Za Side A inverted 3-state output 8 GND 9 /Zb Side B inverted 3-state output 10 I0b Side B data input 0 11 I1b Side B data input 1 12 I2b Side B data input 2 13 I3b Side B data input 3 14 S0 Common Select 0 15 /OEb Side B Output Enable (active LOW) 16 Vcc TRUTH TABLE (each side) ----------------------- S0 S1 I0 I1 I2 I3 /OE /Z -- -- -- -- -- -- --- --- X X X X X X H (Z) L L L X X X L H L L H X X X L L H L X L X X L H H L X H X X L L L H X X L X L H L H X X H X L L H H X X X L L H H H X X X H L L Address inputs S0 and S1 are common to both sections. H = HIGH voltage level; L = LOW voltage level; X = immaterial; (Z) = high impedance. INPUT LOADING / FAN-OUT ----------------------- Pin Names Description U.L. HIGH/LOW --------- --------------------------------------- ------------- I0a - I3a Side A Data Inputs 0.5 / 0.375 I0b - I3b Side B Data Inputs 0.5 / 0.375 S0, S1 Common Select Inputs 0.5 / 0.375 /OEa Side A Output Enable Input (Active LOW) 0.5 / 0.375 /OEb Side B Output Enable Input (Active LOW) 0.5 / 0.375 /Za, /Zb 3-State Outputs (Inverted) 25 / 12.5 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE --------------------------------------------------- Symbol Parameter Min Typ Max Units ------ ---------------------------------- --- ---- --- ----- Icc Power Supply Current, outputs HIGH 8.0 mA Icc Power Supply Current, outputs OFF 15.3 mA Conditions: outputs HIGH -- In, Sn, /OEn = Gnd; Vcc = Max outputs OFF -- In, Sn = Gnd; /OEn = 4.5 V; Vcc = Max AC CHARACTERISTICS ------------------ Symbol Parameter Min Typ Max Units ---------- --------------------------- --- --- --- ----- tPLH Propagation Delay Sn to /Zn -- 6.3 -- ns tPHL Propagation Delay Sn to /Zn -- 6.2 -- ns tPLH Propagation Delay In to /Zn -- 2.9 -- ns tPHL Propagation Delay In to /Zn -- 2.8 -- ns tPZH, tPZL Output Enable Time -- -- -- ns tPHZ, tPLZ Output Disable Time (1) -- -- -- ns (1) Disable times measured with CL = 5 pF.