======================================================================== 74F253 DUAL 4-INPUT MULTIPLEXER (WITH 3-STATE OUTPUTS) ======================================================================== Family: Fairchild FAST (Advanced Schottky TTL) Source: 1980 Fairchild FAST Data Book, pages 4-76 ... 4-78 Status: Released data sheet Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C DESCRIPTION ----------- The 'F253 is a dual 4-input multiplexer with 3-state outputs. It can select two bits of data from four sources using common select inputs. The outputs may be individually switched to a high impedance state with a HIGH on the respective Output Enable (/OE) inputs, allowing the outputs to interface directly with bus oriented systems. o Advanced Schottky process for high speed o Multifunction capability o Non-inverting 3-state outputs FUNCTIONAL DESCRIPTION ---------------------- This device contains two identical 4-input multiplexers with 3-state outputs. They select two bits from four sources selected by common select inputs (S0, S1). The 4-input multiplexers have individual Output Enable (/OEa, /OEb) inputs which, when HIGH, force the outputs to a high impedance (high Z) state. This device is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels supplied to the two select inputs. Za = /OEa * ( I0a*/S1*/S0 + I1a*/S1*S0 + I2a*S1*/S0 + I3a*S1*S0 ) Zb = /OEb * ( I0b*/S1*/S0 + I1b*/S1*S0 + I2b*S1*/S0 + I3b*S1*S0 ) If the outputs of 3-state devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to 3-state devices whose outputs are tied together are designed so that there is no overlap. CONNECTION DIAGRAM (16-pin DIP) ------------------------------- Pin Function Pin Function --- --------------------------- --- --------------------------- 1 /OEa Side A Output Enable 16 Vcc 2 S1 Common Select 1 15 /OEb Side B Output Enable 3 I3a Side A data input 3 14 S0 Common Select 0 4 I2a Side A data input 2 13 I3b Side B data input 3 5 I1a Side A data input 1 12 I2b Side B data input 2 6 I0a Side A data input 0 11 I1b Side B data input 1 7 Za Side A 3-state output 10 I0b Side B data input 0 8 GND 9 Zb Side B 3-state output TRUTH TABLE (each side) ----------------------- S0 S1 I0 I1 I2 I3 /OE Z -- -- -- -- -- -- --- --- X X X X X X H (Z) L L L X X X L L L L H X X X L H H L X L X X L L H L X H X X L H L H X X L X L L L H X X H X L H H H X X X L L L H H X X X H L H Address inputs S0 and S1 are common to both sections. H = HIGH voltage level; L = LOW voltage level; X = immaterial; (Z) = high impedance. INPUT LOADING / FAN-OUT ----------------------- Pin Names Description U.L. HIGH/LOW --------- --------------------------------------- ------------- I0a - I3a Side A Data Inputs 0.5 / 0.375 I0b - I3b Side B Data Inputs 0.5 / 0.375 S0, S1 Common Select Inputs 0.5 / 0.375 /OEa Side A Output Enable Input (Active LOW) 0.5 / 0.375 /OEb Side B Output Enable Input (Active LOW) 0.5 / 0.375 Za, Zb 3-State Outputs 25 / 12.5 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE --------------------------------------------------- Symbol Parameter Min Typ Max Units ------ ---------------------------------- --- --- --- ----- Icc Power Supply Current, outputs HIGH 14 20 mA Icc Power Supply Current, outputs LOW 14 20 mA Icc Power Supply Current, outputs OFF 14 25 mA Conditions: outputs HIGH -- Vcc = Max, /OEn = Gnd; I0, Sn = 4.5 V; I1 - I3 = Gnd outputs LOW -- Vcc = Max; I0, Sn, /OEn = Gnd outputs OFF -- Vcc = Max, /OEn = 4.5 V; I0, Sn = Gnd AC CHARACTERISTICS ------------------ Symbol Parameter Min Typ Max Units ------ -------------------------- --- --- --- ----- tPLH Propagation Delay Sn to Zn 4.0 9.5 13 ns tPHL Propagation Delay Sn to Zn 3.0 8.0 10 ns tPLH Propagation Delay In to Zn 2.0 4.4 6.0 ns tPHL Propagation Delay In to Zn 2.0 4.4 6.0 ns tPZH Output Enable Time 2.0 5.3 7.0 ns tPZL Output Enable Time 2.0 6.5 8.0 ns tPHZ Output Disable Time* 2.0 4.3 6.0 ns tPLZ Output Disable Time* 2.0 4.0 6.0 ns *CL = 5.0 pF