======================================================================== 74F175 QUAD D FLIP-FLOP ======================================================================== Family: Fairchild FAST (Advanced Schottky TTL) Source: 1980 Fairchild FAST Data Book, pages 4-34 ... 4-36 Status: PRELIMINARY -- page 4-34 carries a "Preliminary" watermark. Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C DESCRIPTION ----------- The 'F175 is a high speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW. o Edge-triggered D-type inputs o Buffered positive edge-triggered clock o Asynchronous common reset o True and complement output FUNCTIONAL DESCRIPTION ---------------------- The 'F175 consists of four edge-triggered D flip-flops with individual D inputs and Q and /Q outputs. The Clock and Master Reset are COMMON. The four flip-flops will store the state of their individual D inputs on the LOW-to-HIGH clock (CP) transition, causing individual Q and /Q outputs to follow. A LOW input on the Master Reset (/MR) will force all Q outputs LOW and all /Q outputs HIGH independent of Clock or Data inputs. The 'F175 is useful for general logic applications where a common Master Reset and Clock are acceptable. CONNECTION DIAGRAM (16-pin DIP) ------------------------------- Pin Function Pin Function --- ------------------------------ --- ------------------------------ 1 /MR Master Reset (active LOW) 16 Vcc 2 Q0 True output 0 15 Q3 True output 3 3 /Q0 Complement output 0 14 /Q3 Complement output 3 4 D0 Data input 0 13 D3 Data input 3 5 D1 Data input 1 12 D2 Data input 2 6 /Q1 Complement output 1 11 /Q2 Complement output 2 7 Q1 True output 1 10 Q2 True output 2 8 GND 9 CP Clock Pulse (rising edge) TRUTH TABLE (each flip-flop) ---------------------------- With /MR = H: Input @ tn Outputs @ tn+1 Dn Qn /Qn ---- ---- ---- L L H H H L With /MR = L (asynchronous): all Q = L, all /Q = H, independent of CP and D. tn = bit time before the clock positive-going transition; tn+1 = bit time after the clock positive-going transition. H = HIGH voltage level; L = LOW voltage level. INPUT LOADING / FAN-OUT ----------------------- Pin Names Description U.L. HIGH/LOW ----------- -------------------------------------- ------------- D0 - D3 Data Inputs 0.5 / 0.375 CP Clock Pulse Input (Active Rising Edge) 0.5 / 0.375 /MR Master Reset Input (Active LOW) 0.5 / 0.375 Q0 - Q3 True Outputs 25 / 12.5 /Q0 - /Q3 Complement Outputs 25 / 12.5 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE --------------------------------------------------- Test conditions: Vcc = Max, Dn = /MR = 4.5 V, CP = ^ (rising edge) Symbol Parameter Min Typ Max Units ------ -------------------- --- --- --- ----- ICC Power Supply Current 21 mA AC CHARACTERISTICS ------------------ Symbol Parameter Min Typ Max Units ------ ---------------------------- --- --- --- ----- fmax Maximum Clock Frequency 110 150 -- MHz tPLH Propagation Delay CP to Qn -- 6.1 -- ns tPHL Propagation Delay CP to Qn -- 6.3 -- ns tPHL Propagation Delay /MR to Qn -- 7.2 -- ns tPLH Propagation Delay /MR to /Qn -- 6.4 -- ns AC OPERATING REQUIREMENTS ------------------------- Symbol Parameter Min Typ Max Units ------ ---------------------------- --- --- --- ----- ts (H) Setup Time, HIGH -- Dn to CP 3.0 -- -- ns ts (L) Setup Time, LOW -- Dn to CP 3.0 -- -- ns th (H) Hold Time, HIGH -- Dn to CP 2.0 -- -- ns th (L) Hold Time, LOW -- Dn to CP 2.0 -- -- ns tw (H) CP Pulse Width HIGH 4.5 -- -- ns tw (L) /MR Pulse Width LOW 5.0 -- -- ns trec Recovery Time -- /MR to CP 3.3 -- -- ns