======================================================================== 74F163 SYNCHRONOUS PRESETTABLE BINARY COUNTER (SYNCHRONOUS RESET) ======================================================================== Family: Fairchild FAST (Advanced Schottky TTL) Source: 1980 Fairchild FAST Data Book, pages 4-31 ... 4-33 (shared data sheet with the 'F161, see 54F74F161.txt) Status: PRELIMINARY -- page 4-31 carries a "Preliminary" watermark. Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C DESCRIPTION ----------- The 'F161 and 'F163 are high speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The 'F161 has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. The 'F163 has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock. For dc specifications please refer to the 'F160 data sheet. o SYNCHRONOUS COUNTING AND LOADING o HIGH SPEED SYNCHRONOUS EXPANSION o TYPICAL COUNT FREQUENCY OF 120 MHz FUNCTIONAL DESCRIPTION ---------------------- The 'F160 and 'F162 count modulo-10 in the BCD (8421) sequence. From state 9 (HLLH) they increment to state 0 (LLLL). The 'F161 and 'F163 count modulo-16 in the binary sequence. From state 15 (HHHH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the 'F160 and 'F161) occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset ('F160 and 'F161), synchronous reset ('F162 and 'F163), parallel load, count-up and hold. Five control inputs -- Master Reset (/MR, 'F160 and 'F161), Synchronous Reset (/SR, 'F162 and 'F163), Parallel Enable (/PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) -- determine the mode of operation, as shown in the Mode Select Table. A LOW signal on /MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on /SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on /PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With /PE and /MR ('F160, 'F161) or /SR ('F162, 'F163) HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The 'F160 - 'F163 use D-type edge-triggered flip-flops and changing the /SR, /PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count (TC) output is HIGH when CET is HIGH and the counter is in its maximum count state (9 for the decade counters, 15 for the binary counters). To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers. In the 'F160, 'F162 decade counters, the TC output is fully decoded and can only be HIGH in state 9. If a decade counter is preset to an illegal state, or assumes an illegal state when power is applied, it will return to the normal sequence within two counts, as shown in the state diagram. Logic equations ~~~~~~~~~~~~~~~ Count Enable = CEP * CET * /PE ('F160, 'F162) TC = Q0 * /Q1 * /Q2 * Q3 * CET ('F161, 'F163) TC = Q0 * Q1 * Q2 * Q3 * CET State diagram ~~~~~~~~~~~~~ A simple modulo-16 ring -- there are no illegal states: 0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 6 -> 7 -> 8 -> 9 -> 10 -> 11 -> 12 -> 13 -> 14 -> 15 -> 0 CONNECTION DIAGRAM (16-pin DIP) ------------------------------- Pin Function Pin Function --- -------------------------------------- --- -------------------------- 1 /SR Synchronous Reset 16 Vcc 2 CP Clock Pulse (active rising edge) 15 TC Terminal Count output 3 P0 Parallel data input 0 14 Q0 Flip-flop output 0 4 P1 Parallel data input 1 13 Q1 Flip-flop output 1 5 P2 Parallel data input 2 12 Q2 Flip-flop output 2 6 P3 Parallel data input 3 11 Q3 Flip-flop output 3 7 CEP Count Enable Parallel 10 CET Count Enable Trickle 8 GND 9 /PE Parallel Enable MODE SELECT TABLE ----------------- /SR /PE CET CEP Action on the rising clock edge (^) --- --- --- --- ----------------------------------- L X X X RESET (Clear) H L X X LOAD (Pn -> Qn) H H H H COUNT (Increment) H H L X NO CHANGE (Hold) H H X L NO CHANGE (Hold) H = HIGH voltage level; L = LOW voltage level; X = immaterial. ^ = LOW-to-HIGH transition of CP. INPUT LOADING / FAN-OUT ----------------------- Pin Names Description U.L. HIGH/LOW ----------- -------------------------------------------- ------------- CEP Count Enable Parallel Input 0.5 / 0.375 CET Count Enable Trickle Input 0.5 / 0.75 CP Clock Pulse Input (Active Rising Edge) 0.5 / 0.375 /SR ('F163) Synchronous Reset Input (Active LOW) 0.5 / 0.75 /MR ('F161) Asynchronous Master Reset Input (Active LOW) 0.5 / 0.375 P0 - P3 Parallel Data Inputs 0.5 / 0.375 /PE Parallel Enable Input (Active LOW) 0.5 / 0.75 Q0 - Q3 Flip-flop Outputs 25 / 12.5 TC Terminal Count Output 25 / 12.5 AC CHARACTERISTICS ------------------ Symbol Parameter Min Typ Max Units ------ ------------------------------------- --- --- --- ----- fmax Maximum Count Frequency 100 120 -- MHz tPLH Prop Delay CP to Qn (Load Input HIGH) -- 6.0 -- ns tPHL Prop Delay CP to Qn (Load Input HIGH) -- 7.5 -- ns tPLH Prop Delay CP to Qn (Load Input LOW) -- 6.0 -- ns tPHL Prop Delay CP to Qn (Load Input LOW) -- 7.5 -- ns tPLH Prop Delay CP to TC -- 12 -- ns tPHL Prop Delay CP to TC -- 8.0 -- ns tPLH Prop Delay CET to TC -- 6.5 -- ns tPHL Prop Delay CET to TC -- 6.5 -- ns tPHL Prop Delay /MR to Qn ('F161) -- 10 -- ns AC OPERATING REQUIREMENTS ------------------------- Symbol Parameter Min Typ Max Units ------ ------------------------------------ --- --- --- ----- ts (H) Setup Time, HIGH -- Pn to CP 5.0 -- -- ns ts (L) Setup Time, LOW -- Pn to CP 5.0 -- -- ns th (H) Hold Time, HIGH -- Pn to CP 0 -- -- ns th (L) Hold Time, LOW -- Pn to CP 0 -- -- ns ts (H) Setup Time, HIGH -- /PE or /SR to CP 12 -- -- ns ts (L) Setup Time, LOW -- /PE or /SR to CP 12 -- -- ns th (H) Hold Time, HIGH -- /PE or /SR to CP 0 -- -- ns th (L) Hold Time, LOW -- /PE or /SR to CP 0 -- -- ns ts (H) Setup Time, HIGH -- CEP or CET to CP 9.0 -- -- ns ts (L) Setup Time, LOW -- CEP or CET to CP 9.0 -- -- ns th (H) Hold Time, HIGH -- CEP or CET to CP 0 -- -- ns th (L) Hold Time, LOW -- CEP or CET to CP 0 -- -- ns tw (H) Clock Pulse Width, HIGH 5.0 -- -- ns tw (L) Clock Pulse Width, LOW 5.0 -- -- ns tw (L) /MR Pulse Width LOW ('F161) 10 -- -- ns trec Recovery Time -- /MR to CP ('F161) 6.0 -- -- ns