======================================================================== 74F112 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP ======================================================================== Family: Fairchild FAST (Advanced Schottky TTL) Source: 1985 Fairchild FAST Data Book, pages 4-34 ... 4-36. The 1980 data book carries the 'F112 in its Section 3 selection guide only (page 3-6, description and logic symbol). Status: Released data sheet Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C DESCRIPTION ----------- The 'F112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on /SD or /CD prevents clocking and forces Q or /Q HIGH, respectively. Simultaneous LOW signals on /SD and /CD force both Q and /Q HIGH. Asynchronous Inputs: LOW input to /SD sets Q to HIGH level LOW input to /CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on /CD and /SD makes both Q and /Q HIGH CONNECTION DIAGRAM (16-pin DIP) ------------------------------- Pin Function Pin Function --- -------------------- --- -------------------- 1 /CP1 Clock Pulse 1 16 Vcc 2 K1 15 /CD1 Direct Clear 1 3 J1 14 /CD2 Direct Clear 2 4 /SD1 Direct Set 1 13 /CP2 Clock Pulse 2 5 Q1 12 K2 6 /Q1 11 J2 7 /Q2 10 /SD2 Direct Set 2 8 GND 9 Q2 /CP is active on the falling edge of the clock. TRUTH TABLE (each half) ----------------------- J (@ tn) K (@ tn) Q (@ tn+1) -------- -------- ---------- L L Qn L H L H L H H H /Qn H = HIGH voltage level; L = LOW voltage level. tn = bit time before the clock pulse. tn+1 = bit time after the clock pulse. INPUT LOADING / FAN-OUT ----------------------- Pin Names Description U.L. HIGH/LOW ---------------- ---------------------------------------- ------------- J1, J2, K1, K2 Data Inputs 0.5 / 0.375 /CP1, /CP2 Clock Pulse Inputs (Active Falling Edge) 0.5 / 1.5 /CD1, /CD2 Direct Clear Inputs (Active LOW) 0.5 / 1.875 /SD1, /SD2 Direct Set Inputs (Active LOW) 0.5 / 1.875 Q1, Q2, /Q1, /Q2 Outputs 25 / 12.5 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE --------------------------------------------------- Symbol Parameter Min Typ Max Units Conditions ------ -------------------- --- --- --- ----- ------------------ ICC Power Supply Current 12 19 mA Vcc = Max, VCP = 0 AC CHARACTERISTICS ------------------ TA = +25 C 74F Vcc = +5.0V TA/Vcc = Com Symbol Parameter CL Min Typ Max Min Max Units ------ ----------------------------- ----- --- --- --- --- --- ----- fmax Maximum Clock Frequency -- 110 130 -- 100 -- MHz tPLH Prop Delay /CPn to Qn or /Qn 50 pF 2.0 5.0 6.5 2.0 7.5 ns tPHL Prop Delay /CPn to Qn or /Qn 50 pF 2.0 5.0 6.5 2.0 7.5 ns tPLH Prop Delay /CDn, /SDn to Qn, 50 pF 2.0 4.5 6.5 2.0 7.5 ns /Qn tPHL Prop Delay /CDn, /SDn to Qn, 50 pF 2.0 4.5 6.5 2.0 7.5 ns /Qn AC OPERATING REQUIREMENTS ------------------------- TA = +25 C 74F Vcc = +5.0V TA/Vcc = Com Symbol Parameter Min Typ Max Min Max Units ------ ----------------------------------- --- --- --- --- --- ----- ts (H) Setup Time, HIGH -- Jn or Kn to /CPn 4.0 -- -- 5.0 -- ns ts (L) Setup Time, LOW -- Jn or Kn to /CPn 3.0 -- -- 3.5 -- ns th (H) Hold Time, HIGH -- Jn or Kn to /CPn 0 -- -- 0 -- ns th (L) Hold Time, LOW -- Jn or Kn to /CPn 0 -- -- 0 -- ns tw (H) /CPn Pulse Width, HIGH 4.5 -- -- 5.0 -- ns tw (L) /CPn Pulse Width, LOW 4.5 -- -- 5.0 -- ns tw (L) /CDn or /SDn Pulse Width, LOW 4.5 -- -- 5.0 -- ns trec Recovery Time -- /CDn or /SDn to 4.0 -- -- 5.0 -- ns /CPn