======================================================================== 74F109 DUAL J/K POSITIVE EDGE-TRIGGERED FLIP-FLOP ======================================================================== Family: Fairchild FAST (Advanced Schottky TTL) Source: 1980 Fairchild FAST Data Book, pages 4-14 ... 4-15 Status: PRELIMINARY -- page 4-14 carries a "Preliminary" watermark. Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C DESCRIPTION ----------- The 'F109 consists of two high speed, completely independent transition clocked J/K flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The J/K design allows operation as a D flip-flop (refer to the 'F74 data sheet) by connecting the J and /K inputs together. CONNECTION DIAGRAM (16-pin DIP) ------------------------------- Pin Function Pin Function --- -------------------- --- -------------------- 1 /CD1 Direct Clear 1 16 Vcc 2 J1 15 /CD2 Direct Clear 2 3 /K1 14 J2 4 CP1 Clock Pulse 1 13 /K2 5 /SD1 Direct Set 1 12 CP2 Clock Pulse 2 6 Q1 11 /SD2 Direct Set 2 7 /Q1 10 Q2 8 GND 9 /Q2 TRUTH TABLE (each half) ----------------------- J (@ tn) /K (@ tn) Q (@ tn+1) /Q (@ tn+1) -------- --------- ---------- ----------- L H No Change No Change L L L H H H H L H L Toggles Toggles tn = bit time before the clock pulse; tn+1 = bit time after the clock pulse. H = HIGH voltage level; L = LOW voltage level. No Change = the outputs hold the state they had before the clock pulse. Toggles = the outputs change to the complement of that state. Asynchronous inputs: a LOW input to /SD sets Q to the HIGH level, and a LOW input to /CD sets Q to the LOW level. Clear and Set are independent of the clock. A simultaneous LOW on /CD and /SD makes both Q and /Q HIGH. INPUT LOADING / FAN-OUT ----------------------- Pin Names Description U.L. HIGH/LOW ---------------- --------------------------------------- ------------- J1, J2, /K1, /K2 Data Inputs 0.5 / 0.375 CP1, CP2 Clock Pulse Inputs (Active Rising Edge) 0.5 / 0.375 /CD1, /CD2 Direct Clear Inputs (Active LOW) 0.5 / 1.125 /SD1, /SD2 Direct Set Inputs (Active LOW) 0.5 / 1.125 Q1, Q2, /Q1, /Q2 Outputs 25 / 12.5 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE --------------------------------------------------- Symbol Parameter Min Typ Max Units Conditions ------ -------------------- --- ---- --- ----- -------------------- ICC Power Supply Current 11.7 mA Vcc = Max, VCP = 0 V AC CHARACTERISTICS ------------------ Clock parameters: Symbol Parameter Min Typ Max Units ------ --------------------------- --- --- --- ----- fmax Maximum Clock Frequency -- 125 -- MHz tPLH Prop Delay CPn to Qn or /Qn -- 4.4 -- ns tPHL Prop Delay CPn to Qn or /Qn -- 5.2 -- ns Asynchronous parameters -- propagation delay /CDn or /SDn to Qn or /Qn. Symbol Condition Min Typ Max Units ------ ------------ --- --- --- ----- tPLH VCP >= 2.0 V -- 3.6 -- ns tPHL VCP >= 2.0 V -- 6.5 -- ns tPLH VCP <= 0.8 V -- 2.8 -- ns tPHL VCP <= 0.8 V -- 5.5 -- ns AC OPERATING REQUIREMENTS ------------------------- Symbol Parameter Min Typ Max Units ------ ------------------------------------ --- --- --- ----- ts (H) Setup Time, HIGH -- Jn or /Kn to CPn 2.0 -- -- ns ts (L) Setup Time, LOW -- Jn or /Kn to CPn 3.0 -- -- ns th (H) Hold Time, HIGH -- Jn or /Kn to CPn 1.0 -- -- ns th (L) Hold Time, LOW -- Jn or /Kn to CPn 1.0 -- -- ns tw (H) CPn Pulse Width, HIGH 4.0 -- -- ns tw (L) CPn Pulse Width, LOW 5.0 -- -- ns tw (L) /CDn or /SDn Pulse Width LOW 4.0 -- -- ns trec Recovery Time -- /CDn or /SDn to CP 2.0 -- -- ns