// ============================================================================ // mgpr832.v — REGISTER CARD, 8 x 32-bit, 1 write port / 2 read ports // // GENERATED by tools/netlist2v.py from mgpr832.net — do not edit by hand. // // A structural model of the whole card: every IC (74F240, 74F244, 74F373, // 74F138, 74F86, 74F02) is instantiated from ../74FAST/src and wired exactly // as the KiCad netlist wires it, so the simulation carries the data sheet // propagation delays those models specify. // // Storage is 32 transparent latches ('373), four per register. A latch's LE is // the write strobe for its register, active HIGH, so a register is transparent // while its strobe is asserted and captures on the trailing edge -- this is a // level-sensitive write, not an edge-triggered one. // // Each read port is two inversions deep: the per-register '240s drive an // internal bus with inverted register data, and a second rank of '240s // re-inverts it onto Ab/Bb. Both ranks are 3-state, so Ab/Bb float when that // port's read enable is deasserted. The internal buses are Thevenin terminated // (220R/330R) and idle HIGH, modelled below as `pullup`. // // The output drivers are enabled not by /REA and /REB directly but by the // bank-qualified AEN/BEN: U117 ('86) strap-selects the SEL3 polarity, U119 // ('02) NORs that with the read strobe, and U118 ('240) inverts and buffers // the result out to the drivers. A deselected card therefore releases Ab/Bb // to 3-state instead of driving them, which is what lets two cards share the // read buses. The '138s are gated by the same term on their E3 inputs, so a // deselected card also leaves its internal buses quiet. // // Data pins are permuted between stages for PCB routing (a register's bit 0 is // not the '373's d0); the permutation is carried over verbatim from the // netlist and cancels out by the time data reaches Ab/Bb. // ============================================================================ `timescale 1ns/100ps module mgpr832 ( input wire [3:0] asel, input wire [3:0] bsel, input wire [3:0] ysel, input wire rea_n, input wire reb_n, input wire wr_n, input wire [31:0] y, output wire [31:0] ab, output wire [31:0] bb ); // Bank-select straps JP1 (A read port), JP2 (B read port), JP3 (write port). // // SEL3 is the fourth select bit, which the '138s have no address input for: it // is a bank select, so two cards can share one 16-register address space. Each // JP is a 3-pin header strapping one input of U117 ('86) HIGH (pin 1, pulled up // through R1) or LOW (pin 3); the port's buffered SEL3 is the XOR's other input. // A LOW strap passes SEL3 through, a HIGH strap inverts it, and the XOR output // is LOW when this card is selected -- so each parameter below is simply the // SEL3 level this card answers to. // // There is no "ignore SEL3" setting, so a single-card system must drive SEL3 to // the strapped level rather than leaving it floating. parameter JP1_SEL3 = 1'b0; // A read port parameter JP2_SEL3 = 1'b0; // B read port parameter JP3_SEL3 = 1'b0; // write port // ------------------------------------------------------------------------ // Internal nets, named after the netlist nets they carry // ------------------------------------------------------------------------ wire a0; wire a1; wire a2; wire a3; wire a4; wire a5; wire a6; wire a7; wire a8; wire a9; wire a10; wire a11; wire a12; wire a13; wire a14; wire a15; wire a16; wire a17; wire a18; wire a19; wire a20; wire a21; wire a22; wire a23; wire a24; wire a25; wire a26; wire a27; wire a28; wire a29; wire a30; wire a31; wire aen; wire aen_n; wire asel0b; wire asel1b; wire asel2b; wire asel3b; wire b0; wire b1; wire b2; wire b3; wire b4; wire b5; wire b6; wire b7; wire b8; wire b9; wire b10; wire b11; wire b12; wire b13; wire b14; wire b15; wire b16; wire b17; wire b18; wire b19; wire b20; wire b21; wire b22; wire b23; wire b24; wire b25; wire b26; wire b27; wire b28; wire b29; wire b30; wire b31; wire ben; wire ben_n; wire bsel0b; wire bsel1b; wire bsel2b; wire bsel3b; wire high; wire net_jp1_pin_2; wire net_jp2_pin_2; wire net_jp3_pin_2; wire net_rn57_r3; wire net_u1_i0a; wire net_u1_i0b; wire net_u1_i1a; wire net_u1_i1b; wire net_u1_i2a; wire net_u1_i2b; wire net_u1_i3a; wire net_u1_i3b; wire net_u4_i0a; wire net_u4_i0b; wire net_u4_i1a; wire net_u4_i1b; wire net_u4_i2a; wire net_u4_i2b; wire net_u4_i3a; wire net_u4_i3b; wire net_u7_i0a; wire net_u7_i0b; wire net_u7_i1a; wire net_u7_i1b; wire net_u7_i2a; wire net_u7_i2b; wire net_u7_i3a; wire net_u7_i3b; wire net_u10_i0a; wire net_u10_i0b; wire net_u10_i1a; wire net_u10_i1b; wire net_u10_i2a; wire net_u10_i2b; wire net_u10_i3a; wire net_u10_i3b; wire net_u13_i0a; wire net_u13_i0b; wire net_u13_i1a; wire net_u13_i1b; wire net_u13_i2a; wire net_u13_i2b; wire net_u13_i3a; wire net_u13_i3b; wire net_u16_i0a; wire net_u16_i0b; wire net_u16_i1a; wire net_u16_i1b; wire net_u16_i2a; wire net_u16_i2b; wire net_u16_i3a; wire net_u16_i3b; wire net_u19_i0a; wire net_u19_i0b; wire net_u19_i1a; wire net_u19_i1b; wire net_u19_i2a; wire net_u19_i2b; wire net_u19_i3a; wire net_u19_i3b; wire net_u22_i0a; wire net_u22_i0b; wire net_u22_i1a; wire net_u22_i1b; wire net_u22_i2a; wire net_u22_i2b; wire net_u22_i3a; wire net_u22_i3b; wire net_u25_i0a; wire net_u25_i0b; wire net_u25_i1a; wire net_u25_i1b; wire net_u25_i2a; wire net_u25_i2b; wire net_u25_i3a; wire net_u25_i3b; wire net_u28_i0a; wire net_u28_i0b; wire net_u28_i1a; wire net_u28_i1b; wire net_u28_i2a; wire net_u28_i2b; wire net_u28_i3a; wire net_u28_i3b; wire net_u31_i0a; wire net_u31_i0b; wire net_u31_i1a; wire net_u31_i1b; wire net_u31_i2a; wire net_u31_i2b; wire net_u31_i3a; wire net_u31_i3b; wire net_u34_i0a; wire net_u34_i0b; wire net_u34_i1a; wire net_u34_i1b; wire net_u34_i2a; wire net_u34_i2b; wire net_u34_i3a; wire net_u34_i3b; wire net_u37_i0a; wire net_u37_i0b; wire net_u37_i1a; wire net_u37_i1b; wire net_u37_i2a; wire net_u37_i2b; wire net_u37_i3a; wire net_u37_i3b; wire net_u40_i0a; wire net_u40_i0b; wire net_u40_i1a; wire net_u40_i1b; wire net_u40_i2a; wire net_u40_i2b; wire net_u40_i3a; wire net_u40_i3b; wire net_u43_i0a; wire net_u43_i0b; wire net_u43_i1a; wire net_u43_i1b; wire net_u43_i2a; wire net_u43_i2b; wire net_u43_i3a; wire net_u43_i3b; wire net_u46_i0a; wire net_u46_i0b; wire net_u46_i1a; wire net_u46_i1b; wire net_u46_i2a; wire net_u46_i2b; wire net_u46_i3a; wire net_u46_i3b; wire net_u49_i0a; wire net_u49_i0b; wire net_u49_i1a; wire net_u49_i1b; wire net_u49_i2a; wire net_u49_i2b; wire net_u49_i3a; wire net_u49_i3b; wire net_u52_i0a; wire net_u52_i0b; wire net_u52_i1a; wire net_u52_i1b; wire net_u52_i2a; wire net_u52_i2b; wire net_u52_i3a; wire net_u52_i3b; wire net_u55_i0a; wire net_u55_i0b; wire net_u55_i1a; wire net_u55_i1b; wire net_u55_i2a; wire net_u55_i2b; wire net_u55_i3a; wire net_u55_i3b; wire net_u58_i0a; wire net_u58_i0b; wire net_u58_i1a; wire net_u58_i1b; wire net_u58_i2a; wire net_u58_i2b; wire net_u58_i3a; wire net_u58_i3b; wire net_u61_i0a; wire net_u61_i0b; wire net_u61_i1a; wire net_u61_i1b; wire net_u61_i2a; wire net_u61_i2b; wire net_u61_i3a; wire net_u61_i3b; wire net_u64_i0a; wire net_u64_i0b; wire net_u64_i1a; wire net_u64_i1b; wire net_u64_i2a; wire net_u64_i2b; wire net_u64_i3a; wire net_u64_i3b; wire net_u67_i0a; wire net_u67_i0b; wire net_u67_i1a; wire net_u67_i1b; wire net_u67_i2a; wire net_u67_i2b; wire net_u67_i3a; wire net_u67_i3b; wire net_u70_i0a; wire net_u70_i0b; wire net_u70_i1a; wire net_u70_i1b; wire net_u70_i2a; wire net_u70_i2b; wire net_u70_i3a; wire net_u70_i3b; wire net_u76_i0a; wire net_u76_i0b; wire net_u76_i1a; wire net_u76_i1b; wire net_u76_i2a; wire net_u76_i2b; wire net_u76_i3a; wire net_u76_i3b; wire net_u79_i0a; wire net_u79_i0b; wire net_u79_i1a; wire net_u79_i1b; wire net_u79_i2a; wire net_u79_i2b; wire net_u79_i3a; wire net_u79_i3b; wire net_u82_i0a; wire net_u82_i0b; wire net_u82_i1a; wire net_u82_i1b; wire net_u82_i2a; wire net_u82_i2b; wire net_u82_i3a; wire net_u82_i3b; wire net_u85_i0a; wire net_u85_i0b; wire net_u85_i1a; wire net_u85_i1b; wire net_u85_i2a; wire net_u85_i2b; wire net_u85_i3a; wire net_u85_i3b; wire net_u91_i0a; wire net_u91_i0b; wire net_u91_i1a; wire net_u91_i1b; wire net_u91_i2a; wire net_u91_i2b; wire net_u91_i3a; wire net_u91_i3b; wire net_u94_i0a; wire net_u94_i0b; wire net_u94_i1a; wire net_u94_i1b; wire net_u94_i2a; wire net_u94_i2b; wire net_u94_i3a; wire net_u94_i3b; wire net_u97_i0a; wire net_u97_i0b; wire net_u97_i1a; wire net_u97_i1b; wire net_u97_i2a; wire net_u97_i2b; wire net_u97_i3a; wire net_u97_i3b; wire net_u100_i0a; wire net_u100_i0b; wire net_u100_i1a; wire net_u100_i1b; wire net_u100_i2a; wire net_u100_i2b; wire net_u100_i3a; wire net_u100_i3b; wire net_u117_pad3; wire net_u117_pad6; wire rea0_n; wire rea0b_n; wire rea1_n; wire rea1b_n; wire rea2_n; wire rea2b_n; wire rea3_n; wire rea3b_n; wire rea4_n; wire rea4b_n; wire rea5_n; wire rea5b_n; wire rea6_n; wire rea6b_n; wire rea7_n; wire rea7b_n; wire reab_n; wire reb0_n; wire reb0b_n; wire reb1_n; wire reb1b_n; wire reb2_n; wire reb2b_n; wire reb3_n; wire reb3b_n; wire reb4_n; wire reb4b_n; wire reb5_n; wire reb5b_n; wire reb6_n; wire reb6b_n; wire reb7_n; wire reb7b_n; wire rebb_n; wire wr0_n; wire wr0b_n; wire wr1_n; wire wr1b_n; wire wr2_n; wire wr2b_n; wire wr3_n; wire wr3b_n; wire wr4_n; wire wr4b_n; wire wr5_n; wire wr5b_n; wire wr6_n; wire wr6b_n; wire wr7_n; wire wr7b_n; wire wrb_n; wire yb0; wire yb1; wire yb2; wire yb3; wire yb4; wire yb5; wire yb6; wire yb7; wire yb8; wire yb9; wire yb10; wire yb11; wire yb12; wire yb13; wire yb14; wire yb15; wire yb16; wire yb17; wire yb18; wire yb19; wire yb20; wire yb21; wire yb22; wire yb23; wire yb24; wire yb25; wire yb26; wire yb27; wire yb28; wire yb29; wire yb30; wire yb31; wire yen; wire ysel0b; wire ysel1b; wire ysel2b; wire ysel3b; // Resistor terminations to VCC: a bus with every driver in 3-state // settles HIGH instead of floating. pullup (a0); pullup (a1); pullup (a2); pullup (a3); pullup (a4); pullup (a5); pullup (a6); pullup (a7); pullup (a8); pullup (a9); pullup (a10); pullup (a11); pullup (a12); pullup (a13); pullup (a14); pullup (a15); pullup (a16); pullup (a17); pullup (a18); pullup (a19); pullup (a20); pullup (a21); pullup (a22); pullup (a23); pullup (a24); pullup (a25); pullup (a26); pullup (a27); pullup (a28); pullup (a29); pullup (a30); pullup (a31); pullup (b0); pullup (b1); pullup (b2); pullup (b3); pullup (b4); pullup (b5); pullup (b6); pullup (b7); pullup (b8); pullup (b9); pullup (b10); pullup (b11); pullup (b12); pullup (b13); pullup (b14); pullup (b15); pullup (b16); pullup (b17); pullup (b18); pullup (b19); pullup (b20); pullup (b21); pullup (b22); pullup (b23); pullup (b24); pullup (b25); pullup (b26); pullup (b27); pullup (b28); pullup (b29); pullup (b30); pullup (b31); pullup (high); pullup (net_rn57_r3); pullup (rea0b_n); pullup (rea1b_n); pullup (rea2b_n); pullup (rea3b_n); pullup (rea4b_n); pullup (rea5b_n); pullup (rea6b_n); pullup (rea7b_n); pullup (reab_n); pullup (reb0b_n); pullup (reb1b_n); pullup (reb2b_n); pullup (reb3b_n); pullup (reb4b_n); pullup (reb5b_n); pullup (reb6b_n); pullup (reb7b_n); pullup (rebb_n); pullup (wr0b_n); pullup (wr1b_n); pullup (wr2b_n); pullup (wr3b_n); pullup (wr4b_n); pullup (wr5b_n); pullup (wr6b_n); pullup (wr7b_n); pullup (yb0); pullup (yb1); pullup (yb2); pullup (yb3); pullup (yb4); pullup (yb5); pullup (yb6); pullup (yb7); pullup (yb8); pullup (yb9); pullup (yb10); pullup (yb11); pullup (yb12); pullup (yb13); pullup (yb14); pullup (yb15); pullup (yb16); pullup (yb17); pullup (yb18); pullup (yb19); pullup (yb20); pullup (yb21); pullup (yb22); pullup (yb23); pullup (yb24); pullup (yb25); pullup (yb26); pullup (yb27); pullup (yb28); pullup (yb29); pullup (yb30); pullup (yb31); assign net_jp1_pin_2 = JP1_SEL3; // JP1: A read port responds when SEL3 == JP1_SEL3 assign net_jp2_pin_2 = JP2_SEL3; // JP2: B read port responds when SEL3 == JP2_SEL3 assign net_jp3_pin_2 = JP3_SEL3; // JP3: write port responds when SEL3 == JP3_SEL3 // ------------------------------------------------------------------------ // Input buffers: card control lines and the Y write-data bus // ------------------------------------------------------------------------ f244 u73 ( .oe1_n(1'b0), .d1_1(rea0_n), .o2_4(rea1b_n), .d1_2(rea2_n), .o2_3(rea3b_n), .d1_3(rea4_n), .o2_2(rea5b_n), .d1_4(rea7_n), .o2_1(rea6b_n), .d2_1(rea6_n), .o1_4(rea7b_n), .d2_2(rea5_n), .o1_3(rea4b_n), .d2_3(rea3_n), .o1_2(rea2b_n), .d2_4(rea1_n), .o1_1(rea0b_n), .oe2_n(1'b0) ); f244 u74 ( .oe1_n(1'b0), .d1_1(reb0_n), .o2_4(reb1b_n), .d1_2(reb2_n), .o2_3(reb3b_n), .d1_3(reb4_n), .o2_2(reb5b_n), .d1_4(reb7_n), .o2_1(reb6b_n), .d2_1(reb6_n), .o1_4(reb7b_n), .d2_2(reb5_n), .o1_3(reb4b_n), .d2_3(reb3_n), .o1_2(reb2b_n), .d2_4(reb1_n), .o1_1(reb0b_n), .oe2_n(1'b0) ); f240 u75 ( .oe1_n(1'b0), .d1_1(wr0_n), .o2_4(wr1b_n), .d1_2(wr2_n), .o2_3(wr3b_n), .d1_3(wr4_n), .o2_2(wr5b_n), .d1_4(wr7_n), .o2_1(wr6b_n), .d2_1(wr6_n), .o1_4(wr7b_n), .d2_2(wr5_n), .o1_3(wr4b_n), .d2_3(wr3_n), .o1_2(wr2b_n), .d2_4(wr1_n), .o1_1(wr0b_n), .oe2_n(1'b0) ); f244 u103 ( .oe1_n(1'b0), .d1_1(asel[0]), .o2_4(asel1b), .d1_2(asel[2]), .o2_3(asel3b), .d1_3(rea_n), .o2_2(bsel0b), .d1_4(bsel[1]), .o2_1(bsel2b), .d2_1(bsel[2]), .o1_4(bsel1b), .d2_2(bsel[0]), .o1_3(reab_n), .d2_3(asel[3]), .o1_2(asel2b), .d2_4(asel[1]), .o1_1(asel0b), .oe2_n(1'b0) ); f244 u104 ( .oe1_n(1'b0), .d1_1(bsel[3]), .o2_4(rebb_n), .d1_2(ysel[0]), .o2_3(ysel1b), .d1_3(ysel[2]), .o2_2(ysel3b), .d1_4(wr_n), .o2_1(), .d2_1(high), .o1_4(wrb_n), .d2_2(ysel[3]), .o1_3(ysel2b), .d2_3(ysel[1]), .o1_2(ysel0b), .d2_4(reb_n), .o1_1(bsel3b), .oe2_n(1'b0) ); f244 u107 ( .oe1_n(1'b0), .d1_1(y[0]), .o2_4(yb1), .d1_2(y[2]), .o2_3(yb3), .d1_3(y[4]), .o2_2(yb5), .d1_4(y[6]), .o2_1(yb7), .d2_1(y[7]), .o1_4(yb6), .d2_2(y[5]), .o1_3(yb4), .d2_3(y[3]), .o1_2(yb2), .d2_4(y[1]), .o1_1(yb0), .oe2_n(1'b0) ); f244 u110 ( .oe1_n(1'b0), .d1_1(y[8]), .o2_4(yb9), .d1_2(y[10]), .o2_3(yb11), .d1_3(y[12]), .o2_2(yb13), .d1_4(y[14]), .o2_1(yb15), .d2_1(y[15]), .o1_4(yb14), .d2_2(y[13]), .o1_3(yb12), .d2_3(y[11]), .o1_2(yb10), .d2_4(y[9]), .o1_1(yb8), .oe2_n(1'b0) ); f244 u113 ( .oe1_n(1'b0), .d1_1(y[16]), .o2_4(yb17), .d1_2(y[18]), .o2_3(yb19), .d1_3(y[20]), .o2_2(yb21), .d1_4(y[22]), .o2_1(yb23), .d2_1(y[23]), .o1_4(yb22), .d2_2(y[21]), .o1_3(yb20), .d2_3(y[19]), .o1_2(yb18), .d2_4(y[17]), .o1_1(yb16), .oe2_n(1'b0) ); f244 u116 ( .oe1_n(1'b0), .d1_1(y[24]), .o2_4(yb25), .d1_2(y[26]), .o2_3(yb27), .d1_3(y[28]), .o2_2(yb29), .d1_4(y[30]), .o2_1(yb31), .d2_1(y[31]), .o1_4(yb30), .d2_2(y[29]), .o1_3(yb28), .d2_3(y[27]), .o1_2(yb26), .d2_4(y[25]), .o1_1(yb24), .oe2_n(1'b0) ); // ------------------------------------------------------------------------ // Bank select: SEL3 polarity strap, qualified with the read strobes, buffered out to the output drivers // ------------------------------------------------------------------------ f86 u117 ( .a1(net_jp1_pin_2), .b1(asel3b), .z1(net_u117_pad3), .a2(net_jp2_pin_2), .b2(bsel3b), .z2(net_u117_pad6), .z3(yen), .a3(net_jp3_pin_2), .b3(ysel3b), .z4(), .a4(1'b1), .b4(1'b1) ); f240 u118 ( .oe1_n(1'b0), .d1_1(aen), .o2_4(), .d1_2(ben), .o2_3(), .d1_3(high), .o2_2(), .d1_4(high), .o2_1(), .d2_1(high), .o1_4(), .d2_2(high), .o1_3(), .d2_3(high), .o1_2(ben_n), .d2_4(high), .o1_1(aen_n), .oe2_n(1'b0) ); f02 u119 ( .z1(aen), .a1(net_u117_pad3), .b1(reab_n), .z2(ben), .a2(net_u117_pad6), .b2(rebb_n), .a3(1'b1), .b3(1'b1), .z3(), .a4(1'b1), .b4(1'b1), .z4() ); // ------------------------------------------------------------------------ // Address decoding: one active-LOW strobe per register, per port // ------------------------------------------------------------------------ f138 u88 ( .a0(asel0b), .a1(asel1b), .a2(asel2b), .e1_n(reab_n), .e2_n(1'b0), .e3(aen), .o7_n(rea7_n), .o6_n(rea6_n), .o5_n(rea5_n), .o4_n(rea4_n), .o3_n(rea3_n), .o2_n(rea2_n), .o1_n(rea1_n), .o0_n(rea0_n) ); f138 u89 ( .a0(bsel0b), .a1(bsel1b), .a2(bsel2b), .e1_n(rebb_n), .e2_n(1'b0), .e3(ben), .o7_n(reb7_n), .o6_n(reb6_n), .o5_n(reb5_n), .o4_n(reb4_n), .o3_n(reb3_n), .o2_n(reb2_n), .o1_n(reb1_n), .o0_n(reb0_n) ); f138 u90 ( .a0(ysel0b), .a1(ysel1b), .a2(ysel2b), .e1_n(wrb_n), .e2_n(yen), .e3(high), .o7_n(wr7_n), .o6_n(wr6_n), .o5_n(wr5_n), .o4_n(wr4_n), .o3_n(wr3_n), .o2_n(wr2_n), .o1_n(wr1_n), .o0_n(wr0_n) ); // ------------------------------------------------------------------------ // Register 0: four '373 latches, and the '240s that read them onto the A and B buses // ------------------------------------------------------------------------ f240 u1 ( .oe1_n(rea0b_n), .d1_1(net_u1_i0a), .o2_4(a1), .d1_2(net_u1_i1a), .o2_3(a3), .d1_3(net_u1_i2a), .o2_2(a5), .d1_4(net_u1_i3a), .o2_1(a7), .d2_1(net_u1_i0b), .o1_4(a6), .d2_2(net_u1_i1b), .o1_3(a4), .d2_3(net_u1_i2b), .o1_2(a2), .d2_4(net_u1_i3b), .o1_1(a0), .oe2_n(rea0b_n) ); f240 u2 ( .oe1_n(reb0b_n), .d1_1(net_u1_i0a), .o2_4(b1), .d1_2(net_u1_i1a), .o2_3(b3), .d1_3(net_u1_i2a), .o2_2(b5), .d1_4(net_u1_i3a), .o2_1(b7), .d2_1(net_u1_i0b), .o1_4(b6), .d2_2(net_u1_i1b), .o1_3(b4), .d2_3(net_u1_i2b), .o1_2(b2), .d2_4(net_u1_i3b), .o1_1(b0), .oe2_n(reb0b_n) ); f373 u3 ( .oe_n(1'b0), .o0(net_u1_i0a), .d0(yb0), .d1(yb2), .o1(net_u1_i1a), .o2(net_u1_i2a), .d2(yb4), .d3(yb6), .o3(net_u1_i3a), .le(wr0b_n), .o4(net_u1_i0b), .d4(yb7), .d5(yb5), .o5(net_u1_i1b), .o6(net_u1_i2b), .d6(yb3), .d7(yb1), .o7(net_u1_i3b) ); f240 u4 ( .oe1_n(rea0b_n), .d1_1(net_u4_i0a), .o2_4(a9), .d1_2(net_u4_i1a), .o2_3(a11), .d1_3(net_u4_i2a), .o2_2(a13), .d1_4(net_u4_i3a), .o2_1(a15), .d2_1(net_u4_i0b), .o1_4(a14), .d2_2(net_u4_i1b), .o1_3(a12), .d2_3(net_u4_i2b), .o1_2(a10), .d2_4(net_u4_i3b), .o1_1(a8), .oe2_n(rea0b_n) ); f240 u5 ( .oe1_n(reb0b_n), .d1_1(net_u4_i0a), .o2_4(b9), .d1_2(net_u4_i1a), .o2_3(b11), .d1_3(net_u4_i2a), .o2_2(b13), .d1_4(net_u4_i3a), .o2_1(b15), .d2_1(net_u4_i0b), .o1_4(b14), .d2_2(net_u4_i1b), .o1_3(b12), .d2_3(net_u4_i2b), .o1_2(b10), .d2_4(net_u4_i3b), .o1_1(b8), .oe2_n(reb0b_n) ); f373 u6 ( .oe_n(1'b0), .o0(net_u4_i0a), .d0(yb8), .d1(yb10), .o1(net_u4_i1a), .o2(net_u4_i2a), .d2(yb12), .d3(yb14), .o3(net_u4_i3a), .le(wr0b_n), .o4(net_u4_i0b), .d4(yb15), .d5(yb13), .o5(net_u4_i1b), .o6(net_u4_i2b), .d6(yb11), .d7(yb9), .o7(net_u4_i3b) ); f240 u7 ( .oe1_n(rea0b_n), .d1_1(net_u7_i0a), .o2_4(a17), .d1_2(net_u7_i1a), .o2_3(a19), .d1_3(net_u7_i2a), .o2_2(a21), .d1_4(net_u7_i3a), .o2_1(a23), .d2_1(net_u7_i0b), .o1_4(a22), .d2_2(net_u7_i1b), .o1_3(a20), .d2_3(net_u7_i2b), .o1_2(a18), .d2_4(net_u7_i3b), .o1_1(a16), .oe2_n(rea0b_n) ); f240 u8 ( .oe1_n(reb0b_n), .d1_1(net_u7_i0a), .o2_4(b17), .d1_2(net_u7_i1a), .o2_3(b19), .d1_3(net_u7_i2a), .o2_2(b21), .d1_4(net_u7_i3a), .o2_1(b23), .d2_1(net_u7_i0b), .o1_4(b22), .d2_2(net_u7_i1b), .o1_3(b20), .d2_3(net_u7_i2b), .o1_2(b18), .d2_4(net_u7_i3b), .o1_1(b16), .oe2_n(reb0b_n) ); f373 u9 ( .oe_n(1'b0), .o0(net_u7_i0a), .d0(yb16), .d1(yb18), .o1(net_u7_i1a), .o2(net_u7_i2a), .d2(yb20), .d3(yb22), .o3(net_u7_i3a), .le(wr0b_n), .o4(net_u7_i0b), .d4(yb23), .d5(yb21), .o5(net_u7_i1b), .o6(net_u7_i2b), .d6(yb19), .d7(yb17), .o7(net_u7_i3b) ); f240 u10 ( .oe1_n(rea0b_n), .d1_1(net_u10_i0a), .o2_4(a25), .d1_2(net_u10_i1a), .o2_3(a27), .d1_3(net_u10_i2a), .o2_2(a29), .d1_4(net_u10_i3a), .o2_1(a31), .d2_1(net_u10_i0b), .o1_4(a30), .d2_2(net_u10_i1b), .o1_3(a28), .d2_3(net_u10_i2b), .o1_2(a26), .d2_4(net_u10_i3b), .o1_1(a24), .oe2_n(rea0b_n) ); f240 u11 ( .oe1_n(reb0b_n), .d1_1(net_u10_i0a), .o2_4(b25), .d1_2(net_u10_i1a), .o2_3(b27), .d1_3(net_u10_i2a), .o2_2(b29), .d1_4(net_u10_i3a), .o2_1(b31), .d2_1(net_u10_i0b), .o1_4(b30), .d2_2(net_u10_i1b), .o1_3(b28), .d2_3(net_u10_i2b), .o1_2(b26), .d2_4(net_u10_i3b), .o1_1(b24), .oe2_n(reb0b_n) ); f373 u12 ( .oe_n(1'b0), .o0(net_u10_i0a), .d0(yb24), .d1(yb26), .o1(net_u10_i1a), .o2(net_u10_i2a), .d2(yb28), .d3(yb30), .o3(net_u10_i3a), .le(wr0b_n), .o4(net_u10_i0b), .d4(yb31), .d5(yb29), .o5(net_u10_i1b), .o6(net_u10_i2b), .d6(yb27), .d7(yb25), .o7(net_u10_i3b) ); // ------------------------------------------------------------------------ // Register 1: four '373 latches, and the '240s that read them onto the A and B buses // ------------------------------------------------------------------------ f240 u13 ( .oe1_n(rea1b_n), .d1_1(net_u13_i0a), .o2_4(a1), .d1_2(net_u13_i1a), .o2_3(a3), .d1_3(net_u13_i2a), .o2_2(a5), .d1_4(net_u13_i3a), .o2_1(a7), .d2_1(net_u13_i0b), .o1_4(a6), .d2_2(net_u13_i1b), .o1_3(a4), .d2_3(net_u13_i2b), .o1_2(a2), .d2_4(net_u13_i3b), .o1_1(a0), .oe2_n(rea1b_n) ); f240 u14 ( .oe1_n(reb1b_n), .d1_1(net_u13_i0a), .o2_4(b1), .d1_2(net_u13_i1a), .o2_3(b3), .d1_3(net_u13_i2a), .o2_2(b5), .d1_4(net_u13_i3a), .o2_1(b7), .d2_1(net_u13_i0b), .o1_4(b6), .d2_2(net_u13_i1b), .o1_3(b4), .d2_3(net_u13_i2b), .o1_2(b2), .d2_4(net_u13_i3b), .o1_1(b0), .oe2_n(reb1b_n) ); f373 u15 ( .oe_n(1'b0), .o0(net_u13_i0a), .d0(yb0), .d1(yb2), .o1(net_u13_i1a), .o2(net_u13_i2a), .d2(yb4), .d3(yb6), .o3(net_u13_i3a), .le(wr1b_n), .o4(net_u13_i0b), .d4(yb7), .d5(yb5), .o5(net_u13_i1b), .o6(net_u13_i2b), .d6(yb3), .d7(yb1), .o7(net_u13_i3b) ); f240 u16 ( .oe1_n(rea1b_n), .d1_1(net_u16_i0a), .o2_4(a9), .d1_2(net_u16_i1a), .o2_3(a11), .d1_3(net_u16_i2a), .o2_2(a13), .d1_4(net_u16_i3a), .o2_1(a15), .d2_1(net_u16_i0b), .o1_4(a14), .d2_2(net_u16_i1b), .o1_3(a12), .d2_3(net_u16_i2b), .o1_2(a10), .d2_4(net_u16_i3b), .o1_1(a8), .oe2_n(rea1b_n) ); f240 u17 ( .oe1_n(reb1b_n), .d1_1(net_u16_i0a), .o2_4(b9), .d1_2(net_u16_i1a), .o2_3(b11), .d1_3(net_u16_i2a), .o2_2(b13), .d1_4(net_u16_i3a), .o2_1(b15), .d2_1(net_u16_i0b), .o1_4(b14), .d2_2(net_u16_i1b), .o1_3(b12), .d2_3(net_u16_i2b), .o1_2(b10), .d2_4(net_u16_i3b), .o1_1(b8), .oe2_n(reb1b_n) ); f373 u18 ( .oe_n(1'b0), .o0(net_u16_i0a), .d0(yb8), .d1(yb10), .o1(net_u16_i1a), .o2(net_u16_i2a), .d2(yb12), .d3(yb14), .o3(net_u16_i3a), .le(wr1b_n), .o4(net_u16_i0b), .d4(yb15), .d5(yb13), .o5(net_u16_i1b), .o6(net_u16_i2b), .d6(yb11), .d7(yb9), .o7(net_u16_i3b) ); f240 u19 ( .oe1_n(rea1b_n), .d1_1(net_u19_i0a), .o2_4(a17), .d1_2(net_u19_i1a), .o2_3(a19), .d1_3(net_u19_i2a), .o2_2(a21), .d1_4(net_u19_i3a), .o2_1(a23), .d2_1(net_u19_i0b), .o1_4(a22), .d2_2(net_u19_i1b), .o1_3(a20), .d2_3(net_u19_i2b), .o1_2(a18), .d2_4(net_u19_i3b), .o1_1(a16), .oe2_n(rea1b_n) ); f240 u20 ( .oe1_n(reb1b_n), .d1_1(net_u19_i0a), .o2_4(b17), .d1_2(net_u19_i1a), .o2_3(b19), .d1_3(net_u19_i2a), .o2_2(b21), .d1_4(net_u19_i3a), .o2_1(b23), .d2_1(net_u19_i0b), .o1_4(b22), .d2_2(net_u19_i1b), .o1_3(b20), .d2_3(net_u19_i2b), .o1_2(b18), .d2_4(net_u19_i3b), .o1_1(b16), .oe2_n(reb1b_n) ); f373 u21 ( .oe_n(1'b0), .o0(net_u19_i0a), .d0(yb16), .d1(yb18), .o1(net_u19_i1a), .o2(net_u19_i2a), .d2(yb20), .d3(yb22), .o3(net_u19_i3a), .le(wr1b_n), .o4(net_u19_i0b), .d4(yb23), .d5(yb21), .o5(net_u19_i1b), .o6(net_u19_i2b), .d6(yb19), .d7(yb17), .o7(net_u19_i3b) ); f240 u22 ( .oe1_n(rea1b_n), .d1_1(net_u22_i0a), .o2_4(a25), .d1_2(net_u22_i1a), .o2_3(a27), .d1_3(net_u22_i2a), .o2_2(a29), .d1_4(net_u22_i3a), .o2_1(a31), .d2_1(net_u22_i0b), .o1_4(a30), .d2_2(net_u22_i1b), .o1_3(a28), .d2_3(net_u22_i2b), .o1_2(a26), .d2_4(net_u22_i3b), .o1_1(a24), .oe2_n(rea1b_n) ); f240 u23 ( .oe1_n(reb1b_n), .d1_1(net_u22_i0a), .o2_4(b25), .d1_2(net_u22_i1a), .o2_3(b27), .d1_3(net_u22_i2a), .o2_2(b29), .d1_4(net_u22_i3a), .o2_1(b31), .d2_1(net_u22_i0b), .o1_4(b30), .d2_2(net_u22_i1b), .o1_3(b28), .d2_3(net_u22_i2b), .o1_2(b26), .d2_4(net_u22_i3b), .o1_1(b24), .oe2_n(reb1b_n) ); f373 u24 ( .oe_n(1'b0), .o0(net_u22_i0a), .d0(yb24), .d1(yb26), .o1(net_u22_i1a), .o2(net_u22_i2a), .d2(yb28), .d3(yb30), .o3(net_u22_i3a), .le(wr1b_n), .o4(net_u22_i0b), .d4(yb31), .d5(yb29), .o5(net_u22_i1b), .o6(net_u22_i2b), .d6(yb27), .d7(yb25), .o7(net_u22_i3b) ); // ------------------------------------------------------------------------ // Register 2: four '373 latches, and the '240s that read them onto the A and B buses // ------------------------------------------------------------------------ f240 u25 ( .oe1_n(rea2b_n), .d1_1(net_u25_i0a), .o2_4(a1), .d1_2(net_u25_i1a), .o2_3(a3), .d1_3(net_u25_i2a), .o2_2(a5), .d1_4(net_u25_i3a), .o2_1(a7), .d2_1(net_u25_i0b), .o1_4(a6), .d2_2(net_u25_i1b), .o1_3(a4), .d2_3(net_u25_i2b), .o1_2(a2), .d2_4(net_u25_i3b), .o1_1(a0), .oe2_n(rea2b_n) ); f240 u26 ( .oe1_n(reb2b_n), .d1_1(net_u25_i0a), .o2_4(b1), .d1_2(net_u25_i1a), .o2_3(b3), .d1_3(net_u25_i2a), .o2_2(b5), .d1_4(net_u25_i3a), .o2_1(b7), .d2_1(net_u25_i0b), .o1_4(b6), .d2_2(net_u25_i1b), .o1_3(b4), .d2_3(net_u25_i2b), .o1_2(b2), .d2_4(net_u25_i3b), .o1_1(b0), .oe2_n(reb2b_n) ); f373 u27 ( .oe_n(1'b0), .o0(net_u25_i0a), .d0(yb0), .d1(yb2), .o1(net_u25_i1a), .o2(net_u25_i2a), .d2(yb4), .d3(yb6), .o3(net_u25_i3a), .le(wr2b_n), .o4(net_u25_i0b), .d4(yb7), .d5(yb5), .o5(net_u25_i1b), .o6(net_u25_i2b), .d6(yb3), .d7(yb1), .o7(net_u25_i3b) ); f240 u28 ( .oe1_n(rea2b_n), .d1_1(net_u28_i0a), .o2_4(a9), .d1_2(net_u28_i1a), .o2_3(a11), .d1_3(net_u28_i2a), .o2_2(a13), .d1_4(net_u28_i3a), .o2_1(a15), .d2_1(net_u28_i0b), .o1_4(a14), .d2_2(net_u28_i1b), .o1_3(a12), .d2_3(net_u28_i2b), .o1_2(a10), .d2_4(net_u28_i3b), .o1_1(a8), .oe2_n(rea2b_n) ); f240 u29 ( .oe1_n(reb2b_n), .d1_1(net_u28_i0a), .o2_4(b9), .d1_2(net_u28_i1a), .o2_3(b11), .d1_3(net_u28_i2a), .o2_2(b13), .d1_4(net_u28_i3a), .o2_1(b15), .d2_1(net_u28_i0b), .o1_4(b14), .d2_2(net_u28_i1b), .o1_3(b12), .d2_3(net_u28_i2b), .o1_2(b10), .d2_4(net_u28_i3b), .o1_1(b8), .oe2_n(reb2b_n) ); f373 u30 ( .oe_n(1'b0), .o0(net_u28_i0a), .d0(yb8), .d1(yb10), .o1(net_u28_i1a), .o2(net_u28_i2a), .d2(yb12), .d3(yb14), .o3(net_u28_i3a), .le(wr2b_n), .o4(net_u28_i0b), .d4(yb15), .d5(yb13), .o5(net_u28_i1b), .o6(net_u28_i2b), .d6(yb11), .d7(yb9), .o7(net_u28_i3b) ); f240 u31 ( .oe1_n(rea2b_n), .d1_1(net_u31_i0a), .o2_4(a17), .d1_2(net_u31_i1a), .o2_3(a19), .d1_3(net_u31_i2a), .o2_2(a21), .d1_4(net_u31_i3a), .o2_1(a23), .d2_1(net_u31_i0b), .o1_4(a22), .d2_2(net_u31_i1b), .o1_3(a20), .d2_3(net_u31_i2b), .o1_2(a18), .d2_4(net_u31_i3b), .o1_1(a16), .oe2_n(rea2b_n) ); f240 u32 ( .oe1_n(reb2b_n), .d1_1(net_u31_i0a), .o2_4(b17), .d1_2(net_u31_i1a), .o2_3(b19), .d1_3(net_u31_i2a), .o2_2(b21), .d1_4(net_u31_i3a), .o2_1(b23), .d2_1(net_u31_i0b), .o1_4(b22), .d2_2(net_u31_i1b), .o1_3(b20), .d2_3(net_u31_i2b), .o1_2(b18), .d2_4(net_u31_i3b), .o1_1(b16), .oe2_n(reb2b_n) ); f373 u33 ( .oe_n(1'b0), .o0(net_u31_i0a), .d0(yb16), .d1(yb18), .o1(net_u31_i1a), .o2(net_u31_i2a), .d2(yb20), .d3(yb22), .o3(net_u31_i3a), .le(wr2b_n), .o4(net_u31_i0b), .d4(yb23), .d5(yb21), .o5(net_u31_i1b), .o6(net_u31_i2b), .d6(yb19), .d7(yb17), .o7(net_u31_i3b) ); f240 u34 ( .oe1_n(rea2b_n), .d1_1(net_u34_i0a), .o2_4(a25), .d1_2(net_u34_i1a), .o2_3(a27), .d1_3(net_u34_i2a), .o2_2(a29), .d1_4(net_u34_i3a), .o2_1(a31), .d2_1(net_u34_i0b), .o1_4(a30), .d2_2(net_u34_i1b), .o1_3(a28), .d2_3(net_u34_i2b), .o1_2(a26), .d2_4(net_u34_i3b), .o1_1(a24), .oe2_n(rea2b_n) ); f240 u35 ( .oe1_n(reb2b_n), .d1_1(net_u34_i0a), .o2_4(b25), .d1_2(net_u34_i1a), .o2_3(b27), .d1_3(net_u34_i2a), .o2_2(b29), .d1_4(net_u34_i3a), .o2_1(b31), .d2_1(net_u34_i0b), .o1_4(b30), .d2_2(net_u34_i1b), .o1_3(b28), .d2_3(net_u34_i2b), .o1_2(b26), .d2_4(net_u34_i3b), .o1_1(b24), .oe2_n(reb2b_n) ); f373 u36 ( .oe_n(1'b0), .o0(net_u34_i0a), .d0(yb24), .d1(yb26), .o1(net_u34_i1a), .o2(net_u34_i2a), .d2(yb28), .d3(yb30), .o3(net_u34_i3a), .le(wr2b_n), .o4(net_u34_i0b), .d4(yb31), .d5(yb29), .o5(net_u34_i1b), .o6(net_u34_i2b), .d6(yb27), .d7(yb25), .o7(net_u34_i3b) ); // ------------------------------------------------------------------------ // Register 3: four '373 latches, and the '240s that read them onto the A and B buses // ------------------------------------------------------------------------ f240 u37 ( .oe1_n(rea3b_n), .d1_1(net_u37_i0a), .o2_4(a1), .d1_2(net_u37_i1a), .o2_3(a3), .d1_3(net_u37_i2a), .o2_2(a5), .d1_4(net_u37_i3a), .o2_1(a7), .d2_1(net_u37_i0b), .o1_4(a6), .d2_2(net_u37_i1b), .o1_3(a4), .d2_3(net_u37_i2b), .o1_2(a2), .d2_4(net_u37_i3b), .o1_1(a0), .oe2_n(rea3b_n) ); f240 u38 ( .oe1_n(reb3b_n), .d1_1(net_u37_i0a), .o2_4(b1), .d1_2(net_u37_i1a), .o2_3(b3), .d1_3(net_u37_i2a), .o2_2(b5), .d1_4(net_u37_i3a), .o2_1(b7), .d2_1(net_u37_i0b), .o1_4(b6), .d2_2(net_u37_i1b), .o1_3(b4), .d2_3(net_u37_i2b), .o1_2(b2), .d2_4(net_u37_i3b), .o1_1(b0), .oe2_n(reb3b_n) ); f373 u39 ( .oe_n(1'b0), .o0(net_u37_i0a), .d0(yb0), .d1(yb2), .o1(net_u37_i1a), .o2(net_u37_i2a), .d2(yb4), .d3(yb6), .o3(net_u37_i3a), .le(wr3b_n), .o4(net_u37_i0b), .d4(yb7), .d5(yb5), .o5(net_u37_i1b), .o6(net_u37_i2b), .d6(yb3), .d7(yb1), .o7(net_u37_i3b) ); f240 u40 ( .oe1_n(rea3b_n), .d1_1(net_u40_i0a), .o2_4(a9), .d1_2(net_u40_i1a), .o2_3(a11), .d1_3(net_u40_i2a), .o2_2(a13), .d1_4(net_u40_i3a), .o2_1(a15), .d2_1(net_u40_i0b), .o1_4(a14), .d2_2(net_u40_i1b), .o1_3(a12), .d2_3(net_u40_i2b), .o1_2(a10), .d2_4(net_u40_i3b), .o1_1(a8), .oe2_n(rea3b_n) ); f240 u41 ( .oe1_n(reb3b_n), .d1_1(net_u40_i0a), .o2_4(b9), .d1_2(net_u40_i1a), .o2_3(b11), .d1_3(net_u40_i2a), .o2_2(b13), .d1_4(net_u40_i3a), .o2_1(b15), .d2_1(net_u40_i0b), .o1_4(b14), .d2_2(net_u40_i1b), .o1_3(b12), .d2_3(net_u40_i2b), .o1_2(b10), .d2_4(net_u40_i3b), .o1_1(b8), .oe2_n(reb3b_n) ); f373 u42 ( .oe_n(1'b0), .o0(net_u40_i0a), .d0(yb8), .d1(yb10), .o1(net_u40_i1a), .o2(net_u40_i2a), .d2(yb12), .d3(yb14), .o3(net_u40_i3a), .le(wr3b_n), .o4(net_u40_i0b), .d4(yb15), .d5(yb13), .o5(net_u40_i1b), .o6(net_u40_i2b), .d6(yb11), .d7(yb9), .o7(net_u40_i3b) ); f240 u43 ( .oe1_n(rea3b_n), .d1_1(net_u43_i0a), .o2_4(a17), .d1_2(net_u43_i1a), .o2_3(a19), .d1_3(net_u43_i2a), .o2_2(a21), .d1_4(net_u43_i3a), .o2_1(a23), .d2_1(net_u43_i0b), .o1_4(a22), .d2_2(net_u43_i1b), .o1_3(a20), .d2_3(net_u43_i2b), .o1_2(a18), .d2_4(net_u43_i3b), .o1_1(a16), .oe2_n(rea3b_n) ); f240 u44 ( .oe1_n(reb3b_n), .d1_1(net_u43_i0a), .o2_4(b17), .d1_2(net_u43_i1a), .o2_3(b19), .d1_3(net_u43_i2a), .o2_2(b21), .d1_4(net_u43_i3a), .o2_1(b23), .d2_1(net_u43_i0b), .o1_4(b22), .d2_2(net_u43_i1b), .o1_3(b20), .d2_3(net_u43_i2b), .o1_2(b18), .d2_4(net_u43_i3b), .o1_1(b16), .oe2_n(reb3b_n) ); f373 u45 ( .oe_n(1'b0), .o0(net_u43_i0a), .d0(yb16), .d1(yb18), .o1(net_u43_i1a), .o2(net_u43_i2a), .d2(yb20), .d3(yb22), .o3(net_u43_i3a), .le(wr3b_n), .o4(net_u43_i0b), .d4(yb23), .d5(yb21), .o5(net_u43_i1b), .o6(net_u43_i2b), .d6(yb19), .d7(yb17), .o7(net_u43_i3b) ); f240 u46 ( .oe1_n(rea3b_n), .d1_1(net_u46_i0a), .o2_4(a25), .d1_2(net_u46_i1a), .o2_3(a27), .d1_3(net_u46_i2a), .o2_2(a29), .d1_4(net_u46_i3a), .o2_1(a31), .d2_1(net_u46_i0b), .o1_4(a30), .d2_2(net_u46_i1b), .o1_3(a28), .d2_3(net_u46_i2b), .o1_2(a26), .d2_4(net_u46_i3b), .o1_1(a24), .oe2_n(rea3b_n) ); f240 u47 ( .oe1_n(reb3b_n), .d1_1(net_u46_i0a), .o2_4(b25), .d1_2(net_u46_i1a), .o2_3(b27), .d1_3(net_u46_i2a), .o2_2(b29), .d1_4(net_u46_i3a), .o2_1(b31), .d2_1(net_u46_i0b), .o1_4(b30), .d2_2(net_u46_i1b), .o1_3(b28), .d2_3(net_u46_i2b), .o1_2(b26), .d2_4(net_u46_i3b), .o1_1(b24), .oe2_n(reb3b_n) ); f373 u48 ( .oe_n(1'b0), .o0(net_u46_i0a), .d0(yb24), .d1(yb26), .o1(net_u46_i1a), .o2(net_u46_i2a), .d2(yb28), .d3(yb30), .o3(net_u46_i3a), .le(wr3b_n), .o4(net_u46_i0b), .d4(yb31), .d5(yb29), .o5(net_u46_i1b), .o6(net_u46_i2b), .d6(yb27), .d7(yb25), .o7(net_u46_i3b) ); // ------------------------------------------------------------------------ // Register 4: four '373 latches, and the '240s that read them onto the A and B buses // ------------------------------------------------------------------------ f240 u49 ( .oe1_n(rea4b_n), .d1_1(net_u49_i0a), .o2_4(a1), .d1_2(net_u49_i1a), .o2_3(a3), .d1_3(net_u49_i2a), .o2_2(a5), .d1_4(net_u49_i3a), .o2_1(a7), .d2_1(net_u49_i0b), .o1_4(a6), .d2_2(net_u49_i1b), .o1_3(a4), .d2_3(net_u49_i2b), .o1_2(a2), .d2_4(net_u49_i3b), .o1_1(a0), .oe2_n(rea4b_n) ); f240 u50 ( .oe1_n(reb4b_n), .d1_1(net_u49_i0a), .o2_4(b1), .d1_2(net_u49_i1a), .o2_3(b3), .d1_3(net_u49_i2a), .o2_2(b5), .d1_4(net_u49_i3a), .o2_1(b7), .d2_1(net_u49_i0b), .o1_4(b6), .d2_2(net_u49_i1b), .o1_3(b4), .d2_3(net_u49_i2b), .o1_2(b2), .d2_4(net_u49_i3b), .o1_1(b0), .oe2_n(reb4b_n) ); f373 u51 ( .oe_n(1'b0), .o0(net_u49_i0a), .d0(yb0), .d1(yb2), .o1(net_u49_i1a), .o2(net_u49_i2a), .d2(yb4), .d3(yb6), .o3(net_u49_i3a), .le(wr4b_n), .o4(net_u49_i0b), .d4(yb7), .d5(yb5), .o5(net_u49_i1b), .o6(net_u49_i2b), .d6(yb3), .d7(yb1), .o7(net_u49_i3b) ); f240 u52 ( .oe1_n(rea4b_n), .d1_1(net_u52_i0a), .o2_4(a9), .d1_2(net_u52_i1a), .o2_3(a11), .d1_3(net_u52_i2a), .o2_2(a13), .d1_4(net_u52_i3a), .o2_1(a15), .d2_1(net_u52_i0b), .o1_4(a14), .d2_2(net_u52_i1b), .o1_3(a12), .d2_3(net_u52_i2b), .o1_2(a10), .d2_4(net_u52_i3b), .o1_1(a8), .oe2_n(rea4b_n) ); f240 u53 ( .oe1_n(reb4b_n), .d1_1(net_u52_i0a), .o2_4(b9), .d1_2(net_u52_i1a), .o2_3(b11), .d1_3(net_u52_i2a), .o2_2(b13), .d1_4(net_u52_i3a), .o2_1(b15), .d2_1(net_u52_i0b), .o1_4(b14), .d2_2(net_u52_i1b), .o1_3(b12), .d2_3(net_u52_i2b), .o1_2(b10), .d2_4(net_u52_i3b), .o1_1(b8), .oe2_n(reb4b_n) ); f373 u54 ( .oe_n(1'b0), .o0(net_u52_i0a), .d0(yb8), .d1(yb10), .o1(net_u52_i1a), .o2(net_u52_i2a), .d2(yb12), .d3(yb14), .o3(net_u52_i3a), .le(wr4b_n), .o4(net_u52_i0b), .d4(yb15), .d5(yb13), .o5(net_u52_i1b), .o6(net_u52_i2b), .d6(yb11), .d7(yb9), .o7(net_u52_i3b) ); f240 u55 ( .oe1_n(rea4b_n), .d1_1(net_u55_i0a), .o2_4(a17), .d1_2(net_u55_i1a), .o2_3(a19), .d1_3(net_u55_i2a), .o2_2(a21), .d1_4(net_u55_i3a), .o2_1(a23), .d2_1(net_u55_i0b), .o1_4(a22), .d2_2(net_u55_i1b), .o1_3(a20), .d2_3(net_u55_i2b), .o1_2(a18), .d2_4(net_u55_i3b), .o1_1(a16), .oe2_n(rea4b_n) ); f240 u56 ( .oe1_n(reb4b_n), .d1_1(net_u55_i0a), .o2_4(b17), .d1_2(net_u55_i1a), .o2_3(b19), .d1_3(net_u55_i2a), .o2_2(b21), .d1_4(net_u55_i3a), .o2_1(b23), .d2_1(net_u55_i0b), .o1_4(b22), .d2_2(net_u55_i1b), .o1_3(b20), .d2_3(net_u55_i2b), .o1_2(b18), .d2_4(net_u55_i3b), .o1_1(b16), .oe2_n(reb4b_n) ); f373 u57 ( .oe_n(1'b0), .o0(net_u55_i0a), .d0(yb16), .d1(yb18), .o1(net_u55_i1a), .o2(net_u55_i2a), .d2(yb20), .d3(yb22), .o3(net_u55_i3a), .le(wr4b_n), .o4(net_u55_i0b), .d4(yb23), .d5(yb21), .o5(net_u55_i1b), .o6(net_u55_i2b), .d6(yb19), .d7(yb17), .o7(net_u55_i3b) ); f240 u58 ( .oe1_n(rea4b_n), .d1_1(net_u58_i0a), .o2_4(a25), .d1_2(net_u58_i1a), .o2_3(a27), .d1_3(net_u58_i2a), .o2_2(a29), .d1_4(net_u58_i3a), .o2_1(a31), .d2_1(net_u58_i0b), .o1_4(a30), .d2_2(net_u58_i1b), .o1_3(a28), .d2_3(net_u58_i2b), .o1_2(a26), .d2_4(net_u58_i3b), .o1_1(a24), .oe2_n(rea4b_n) ); f240 u59 ( .oe1_n(reb4b_n), .d1_1(net_u58_i0a), .o2_4(b25), .d1_2(net_u58_i1a), .o2_3(b27), .d1_3(net_u58_i2a), .o2_2(b29), .d1_4(net_u58_i3a), .o2_1(b31), .d2_1(net_u58_i0b), .o1_4(b30), .d2_2(net_u58_i1b), .o1_3(b28), .d2_3(net_u58_i2b), .o1_2(b26), .d2_4(net_u58_i3b), .o1_1(b24), .oe2_n(reb4b_n) ); f373 u60 ( .oe_n(1'b0), .o0(net_u58_i0a), .d0(yb24), .d1(yb26), .o1(net_u58_i1a), .o2(net_u58_i2a), .d2(yb28), .d3(yb30), .o3(net_u58_i3a), .le(wr4b_n), .o4(net_u58_i0b), .d4(yb31), .d5(yb29), .o5(net_u58_i1b), .o6(net_u58_i2b), .d6(yb27), .d7(yb25), .o7(net_u58_i3b) ); // ------------------------------------------------------------------------ // Register 5: four '373 latches, and the '240s that read them onto the A and B buses // ------------------------------------------------------------------------ f240 u61 ( .oe1_n(rea5b_n), .d1_1(net_u61_i0a), .o2_4(a1), .d1_2(net_u61_i1a), .o2_3(a3), .d1_3(net_u61_i2a), .o2_2(a5), .d1_4(net_u61_i3a), .o2_1(a7), .d2_1(net_u61_i0b), .o1_4(a6), .d2_2(net_u61_i1b), .o1_3(a4), .d2_3(net_u61_i2b), .o1_2(a2), .d2_4(net_u61_i3b), .o1_1(a0), .oe2_n(rea5b_n) ); f240 u62 ( .oe1_n(reb5b_n), .d1_1(net_u61_i0a), .o2_4(b1), .d1_2(net_u61_i1a), .o2_3(b3), .d1_3(net_u61_i2a), .o2_2(b5), .d1_4(net_u61_i3a), .o2_1(b7), .d2_1(net_u61_i0b), .o1_4(b6), .d2_2(net_u61_i1b), .o1_3(b4), .d2_3(net_u61_i2b), .o1_2(b2), .d2_4(net_u61_i3b), .o1_1(b0), .oe2_n(reb5b_n) ); f373 u63 ( .oe_n(1'b0), .o0(net_u61_i0a), .d0(yb0), .d1(yb2), .o1(net_u61_i1a), .o2(net_u61_i2a), .d2(yb4), .d3(yb6), .o3(net_u61_i3a), .le(wr5b_n), .o4(net_u61_i0b), .d4(yb7), .d5(yb5), .o5(net_u61_i1b), .o6(net_u61_i2b), .d6(yb3), .d7(yb1), .o7(net_u61_i3b) ); f240 u64 ( .oe1_n(rea5b_n), .d1_1(net_u64_i0a), .o2_4(a9), .d1_2(net_u64_i1a), .o2_3(a11), .d1_3(net_u64_i2a), .o2_2(a13), .d1_4(net_u64_i3a), .o2_1(a15), .d2_1(net_u64_i0b), .o1_4(a14), .d2_2(net_u64_i1b), .o1_3(a12), .d2_3(net_u64_i2b), .o1_2(a10), .d2_4(net_u64_i3b), .o1_1(a8), .oe2_n(rea5b_n) ); f240 u65 ( .oe1_n(reb5b_n), .d1_1(net_u64_i0a), .o2_4(b9), .d1_2(net_u64_i1a), .o2_3(b11), .d1_3(net_u64_i2a), .o2_2(b13), .d1_4(net_u64_i3a), .o2_1(b15), .d2_1(net_u64_i0b), .o1_4(b14), .d2_2(net_u64_i1b), .o1_3(b12), .d2_3(net_u64_i2b), .o1_2(b10), .d2_4(net_u64_i3b), .o1_1(b8), .oe2_n(reb5b_n) ); f373 u66 ( .oe_n(1'b0), .o0(net_u64_i0a), .d0(yb8), .d1(yb10), .o1(net_u64_i1a), .o2(net_u64_i2a), .d2(yb12), .d3(yb14), .o3(net_u64_i3a), .le(wr5b_n), .o4(net_u64_i0b), .d4(yb15), .d5(yb13), .o5(net_u64_i1b), .o6(net_u64_i2b), .d6(yb11), .d7(yb9), .o7(net_u64_i3b) ); f240 u67 ( .oe1_n(rea5b_n), .d1_1(net_u67_i0a), .o2_4(a17), .d1_2(net_u67_i1a), .o2_3(a19), .d1_3(net_u67_i2a), .o2_2(a21), .d1_4(net_u67_i3a), .o2_1(a23), .d2_1(net_u67_i0b), .o1_4(a22), .d2_2(net_u67_i1b), .o1_3(a20), .d2_3(net_u67_i2b), .o1_2(a18), .d2_4(net_u67_i3b), .o1_1(a16), .oe2_n(rea5b_n) ); f240 u68 ( .oe1_n(reb5b_n), .d1_1(net_u67_i0a), .o2_4(b17), .d1_2(net_u67_i1a), .o2_3(b19), .d1_3(net_u67_i2a), .o2_2(b21), .d1_4(net_u67_i3a), .o2_1(b23), .d2_1(net_u67_i0b), .o1_4(b22), .d2_2(net_u67_i1b), .o1_3(b20), .d2_3(net_u67_i2b), .o1_2(b18), .d2_4(net_u67_i3b), .o1_1(b16), .oe2_n(reb5b_n) ); f373 u69 ( .oe_n(1'b0), .o0(net_u67_i0a), .d0(yb16), .d1(yb18), .o1(net_u67_i1a), .o2(net_u67_i2a), .d2(yb20), .d3(yb22), .o3(net_u67_i3a), .le(wr5b_n), .o4(net_u67_i0b), .d4(yb23), .d5(yb21), .o5(net_u67_i1b), .o6(net_u67_i2b), .d6(yb19), .d7(yb17), .o7(net_u67_i3b) ); f240 u70 ( .oe1_n(rea5b_n), .d1_1(net_u70_i0a), .o2_4(a25), .d1_2(net_u70_i1a), .o2_3(a27), .d1_3(net_u70_i2a), .o2_2(a29), .d1_4(net_u70_i3a), .o2_1(a31), .d2_1(net_u70_i0b), .o1_4(a30), .d2_2(net_u70_i1b), .o1_3(a28), .d2_3(net_u70_i2b), .o1_2(a26), .d2_4(net_u70_i3b), .o1_1(a24), .oe2_n(rea5b_n) ); f240 u71 ( .oe1_n(reb5b_n), .d1_1(net_u70_i0a), .o2_4(b25), .d1_2(net_u70_i1a), .o2_3(b27), .d1_3(net_u70_i2a), .o2_2(b29), .d1_4(net_u70_i3a), .o2_1(b31), .d2_1(net_u70_i0b), .o1_4(b30), .d2_2(net_u70_i1b), .o1_3(b28), .d2_3(net_u70_i2b), .o1_2(b26), .d2_4(net_u70_i3b), .o1_1(b24), .oe2_n(reb5b_n) ); f373 u72 ( .oe_n(1'b0), .o0(net_u70_i0a), .d0(yb24), .d1(yb26), .o1(net_u70_i1a), .o2(net_u70_i2a), .d2(yb28), .d3(yb30), .o3(net_u70_i3a), .le(wr5b_n), .o4(net_u70_i0b), .d4(yb31), .d5(yb29), .o5(net_u70_i1b), .o6(net_u70_i2b), .d6(yb27), .d7(yb25), .o7(net_u70_i3b) ); // ------------------------------------------------------------------------ // Register 6: four '373 latches, and the '240s that read them onto the A and B buses // ------------------------------------------------------------------------ f240 u76 ( .oe1_n(rea6b_n), .d1_1(net_u76_i0a), .o2_4(a1), .d1_2(net_u76_i1a), .o2_3(a3), .d1_3(net_u76_i2a), .o2_2(a5), .d1_4(net_u76_i3a), .o2_1(a7), .d2_1(net_u76_i0b), .o1_4(a6), .d2_2(net_u76_i1b), .o1_3(a4), .d2_3(net_u76_i2b), .o1_2(a2), .d2_4(net_u76_i3b), .o1_1(a0), .oe2_n(rea6b_n) ); f240 u77 ( .oe1_n(reb6b_n), .d1_1(net_u76_i0a), .o2_4(b1), .d1_2(net_u76_i1a), .o2_3(b3), .d1_3(net_u76_i2a), .o2_2(b5), .d1_4(net_u76_i3a), .o2_1(b7), .d2_1(net_u76_i0b), .o1_4(b6), .d2_2(net_u76_i1b), .o1_3(b4), .d2_3(net_u76_i2b), .o1_2(b2), .d2_4(net_u76_i3b), .o1_1(b0), .oe2_n(reb6b_n) ); f373 u78 ( .oe_n(1'b0), .o0(net_u76_i0a), .d0(yb0), .d1(yb2), .o1(net_u76_i1a), .o2(net_u76_i2a), .d2(yb4), .d3(yb6), .o3(net_u76_i3a), .le(wr6b_n), .o4(net_u76_i0b), .d4(yb7), .d5(yb5), .o5(net_u76_i1b), .o6(net_u76_i2b), .d6(yb3), .d7(yb1), .o7(net_u76_i3b) ); f240 u79 ( .oe1_n(rea6b_n), .d1_1(net_u79_i0a), .o2_4(a9), .d1_2(net_u79_i1a), .o2_3(a11), .d1_3(net_u79_i2a), .o2_2(a13), .d1_4(net_u79_i3a), .o2_1(a15), .d2_1(net_u79_i0b), .o1_4(a14), .d2_2(net_u79_i1b), .o1_3(a12), .d2_3(net_u79_i2b), .o1_2(a10), .d2_4(net_u79_i3b), .o1_1(a8), .oe2_n(rea6b_n) ); f240 u80 ( .oe1_n(reb6b_n), .d1_1(net_u79_i0a), .o2_4(b9), .d1_2(net_u79_i1a), .o2_3(b11), .d1_3(net_u79_i2a), .o2_2(b13), .d1_4(net_u79_i3a), .o2_1(b15), .d2_1(net_u79_i0b), .o1_4(b14), .d2_2(net_u79_i1b), .o1_3(b12), .d2_3(net_u79_i2b), .o1_2(b10), .d2_4(net_u79_i3b), .o1_1(b8), .oe2_n(reb6b_n) ); f373 u81 ( .oe_n(1'b0), .o0(net_u79_i0a), .d0(yb8), .d1(yb10), .o1(net_u79_i1a), .o2(net_u79_i2a), .d2(yb12), .d3(yb14), .o3(net_u79_i3a), .le(wr6b_n), .o4(net_u79_i0b), .d4(yb15), .d5(yb13), .o5(net_u79_i1b), .o6(net_u79_i2b), .d6(yb11), .d7(yb9), .o7(net_u79_i3b) ); f240 u82 ( .oe1_n(rea6b_n), .d1_1(net_u82_i0a), .o2_4(a17), .d1_2(net_u82_i1a), .o2_3(a19), .d1_3(net_u82_i2a), .o2_2(a21), .d1_4(net_u82_i3a), .o2_1(a23), .d2_1(net_u82_i0b), .o1_4(a22), .d2_2(net_u82_i1b), .o1_3(a20), .d2_3(net_u82_i2b), .o1_2(a18), .d2_4(net_u82_i3b), .o1_1(a16), .oe2_n(rea6b_n) ); f240 u83 ( .oe1_n(reb6b_n), .d1_1(net_u82_i0a), .o2_4(b17), .d1_2(net_u82_i1a), .o2_3(b19), .d1_3(net_u82_i2a), .o2_2(b21), .d1_4(net_u82_i3a), .o2_1(b23), .d2_1(net_u82_i0b), .o1_4(b22), .d2_2(net_u82_i1b), .o1_3(b20), .d2_3(net_u82_i2b), .o1_2(b18), .d2_4(net_u82_i3b), .o1_1(b16), .oe2_n(reb6b_n) ); f373 u84 ( .oe_n(1'b0), .o0(net_u82_i0a), .d0(yb16), .d1(yb18), .o1(net_u82_i1a), .o2(net_u82_i2a), .d2(yb20), .d3(yb22), .o3(net_u82_i3a), .le(wr6b_n), .o4(net_u82_i0b), .d4(yb23), .d5(yb21), .o5(net_u82_i1b), .o6(net_u82_i2b), .d6(yb19), .d7(yb17), .o7(net_u82_i3b) ); f240 u85 ( .oe1_n(rea6b_n), .d1_1(net_u85_i0a), .o2_4(a25), .d1_2(net_u85_i1a), .o2_3(a27), .d1_3(net_u85_i2a), .o2_2(a29), .d1_4(net_u85_i3a), .o2_1(a31), .d2_1(net_u85_i0b), .o1_4(a30), .d2_2(net_u85_i1b), .o1_3(a28), .d2_3(net_u85_i2b), .o1_2(a26), .d2_4(net_u85_i3b), .o1_1(a24), .oe2_n(rea6b_n) ); f240 u86 ( .oe1_n(reb6b_n), .d1_1(net_u85_i0a), .o2_4(b25), .d1_2(net_u85_i1a), .o2_3(b27), .d1_3(net_u85_i2a), .o2_2(b29), .d1_4(net_u85_i3a), .o2_1(b31), .d2_1(net_u85_i0b), .o1_4(b30), .d2_2(net_u85_i1b), .o1_3(b28), .d2_3(net_u85_i2b), .o1_2(b26), .d2_4(net_u85_i3b), .o1_1(b24), .oe2_n(reb6b_n) ); f373 u87 ( .oe_n(1'b0), .o0(net_u85_i0a), .d0(yb24), .d1(yb26), .o1(net_u85_i1a), .o2(net_u85_i2a), .d2(yb28), .d3(yb30), .o3(net_u85_i3a), .le(wr6b_n), .o4(net_u85_i0b), .d4(yb31), .d5(yb29), .o5(net_u85_i1b), .o6(net_u85_i2b), .d6(yb27), .d7(yb25), .o7(net_u85_i3b) ); // ------------------------------------------------------------------------ // Register 7: four '373 latches, and the '240s that read them onto the A and B buses // ------------------------------------------------------------------------ f240 u91 ( .oe1_n(rea7b_n), .d1_1(net_u91_i0a), .o2_4(a1), .d1_2(net_u91_i1a), .o2_3(a3), .d1_3(net_u91_i2a), .o2_2(a5), .d1_4(net_u91_i3a), .o2_1(a7), .d2_1(net_u91_i0b), .o1_4(a6), .d2_2(net_u91_i1b), .o1_3(a4), .d2_3(net_u91_i2b), .o1_2(a2), .d2_4(net_u91_i3b), .o1_1(a0), .oe2_n(rea7b_n) ); f240 u92 ( .oe1_n(reb7b_n), .d1_1(net_u91_i0a), .o2_4(b1), .d1_2(net_u91_i1a), .o2_3(b3), .d1_3(net_u91_i2a), .o2_2(b5), .d1_4(net_u91_i3a), .o2_1(b7), .d2_1(net_u91_i0b), .o1_4(b6), .d2_2(net_u91_i1b), .o1_3(b4), .d2_3(net_u91_i2b), .o1_2(b2), .d2_4(net_u91_i3b), .o1_1(b0), .oe2_n(reb7b_n) ); f373 u93 ( .oe_n(1'b0), .o0(net_u91_i0a), .d0(yb0), .d1(yb2), .o1(net_u91_i1a), .o2(net_u91_i2a), .d2(yb4), .d3(yb6), .o3(net_u91_i3a), .le(wr7b_n), .o4(net_u91_i0b), .d4(yb7), .d5(yb5), .o5(net_u91_i1b), .o6(net_u91_i2b), .d6(yb3), .d7(yb1), .o7(net_u91_i3b) ); f240 u94 ( .oe1_n(rea7b_n), .d1_1(net_u94_i0a), .o2_4(a9), .d1_2(net_u94_i1a), .o2_3(a11), .d1_3(net_u94_i2a), .o2_2(a13), .d1_4(net_u94_i3a), .o2_1(a15), .d2_1(net_u94_i0b), .o1_4(a14), .d2_2(net_u94_i1b), .o1_3(a12), .d2_3(net_u94_i2b), .o1_2(a10), .d2_4(net_u94_i3b), .o1_1(a8), .oe2_n(rea7b_n) ); f240 u95 ( .oe1_n(reb7b_n), .d1_1(net_u94_i0a), .o2_4(b9), .d1_2(net_u94_i1a), .o2_3(b11), .d1_3(net_u94_i2a), .o2_2(b13), .d1_4(net_u94_i3a), .o2_1(b15), .d2_1(net_u94_i0b), .o1_4(b14), .d2_2(net_u94_i1b), .o1_3(b12), .d2_3(net_u94_i2b), .o1_2(b10), .d2_4(net_u94_i3b), .o1_1(b8), .oe2_n(reb7b_n) ); f373 u96 ( .oe_n(1'b0), .o0(net_u94_i0a), .d0(yb8), .d1(yb10), .o1(net_u94_i1a), .o2(net_u94_i2a), .d2(yb12), .d3(yb14), .o3(net_u94_i3a), .le(wr7b_n), .o4(net_u94_i0b), .d4(yb15), .d5(yb13), .o5(net_u94_i1b), .o6(net_u94_i2b), .d6(yb11), .d7(yb9), .o7(net_u94_i3b) ); f240 u97 ( .oe1_n(rea7b_n), .d1_1(net_u97_i0a), .o2_4(a17), .d1_2(net_u97_i1a), .o2_3(a19), .d1_3(net_u97_i2a), .o2_2(a21), .d1_4(net_u97_i3a), .o2_1(a23), .d2_1(net_u97_i0b), .o1_4(a22), .d2_2(net_u97_i1b), .o1_3(a20), .d2_3(net_u97_i2b), .o1_2(a18), .d2_4(net_u97_i3b), .o1_1(a16), .oe2_n(rea7b_n) ); f240 u98 ( .oe1_n(reb7b_n), .d1_1(net_u97_i0a), .o2_4(b17), .d1_2(net_u97_i1a), .o2_3(b19), .d1_3(net_u97_i2a), .o2_2(b21), .d1_4(net_u97_i3a), .o2_1(b23), .d2_1(net_u97_i0b), .o1_4(b22), .d2_2(net_u97_i1b), .o1_3(b20), .d2_3(net_u97_i2b), .o1_2(b18), .d2_4(net_u97_i3b), .o1_1(b16), .oe2_n(reb7b_n) ); f373 u99 ( .oe_n(1'b0), .o0(net_u97_i0a), .d0(yb16), .d1(yb18), .o1(net_u97_i1a), .o2(net_u97_i2a), .d2(yb20), .d3(yb22), .o3(net_u97_i3a), .le(wr7b_n), .o4(net_u97_i0b), .d4(yb23), .d5(yb21), .o5(net_u97_i1b), .o6(net_u97_i2b), .d6(yb19), .d7(yb17), .o7(net_u97_i3b) ); f240 u100 ( .oe1_n(rea7b_n), .d1_1(net_u100_i0a), .o2_4(a25), .d1_2(net_u100_i1a), .o2_3(a27), .d1_3(net_u100_i2a), .o2_2(a29), .d1_4(net_u100_i3a), .o2_1(a31), .d2_1(net_u100_i0b), .o1_4(a30), .d2_2(net_u100_i1b), .o1_3(a28), .d2_3(net_u100_i2b), .o1_2(a26), .d2_4(net_u100_i3b), .o1_1(a24), .oe2_n(rea7b_n) ); f240 u101 ( .oe1_n(reb7b_n), .d1_1(net_u100_i0a), .o2_4(b25), .d1_2(net_u100_i1a), .o2_3(b27), .d1_3(net_u100_i2a), .o2_2(b29), .d1_4(net_u100_i3a), .o2_1(b31), .d2_1(net_u100_i0b), .o1_4(b30), .d2_2(net_u100_i1b), .o1_3(b28), .d2_3(net_u100_i2b), .o1_2(b26), .d2_4(net_u100_i3b), .o1_1(b24), .oe2_n(reb7b_n) ); f373 u102 ( .oe_n(1'b0), .o0(net_u100_i0a), .d0(yb24), .d1(yb26), .o1(net_u100_i1a), .o2(net_u100_i2a), .d2(yb28), .d3(yb30), .o3(net_u100_i3a), .le(wr7b_n), .o4(net_u100_i0b), .d4(yb31), .d5(yb29), .o5(net_u100_i1b), .o6(net_u100_i2b), .d6(yb27), .d7(yb25), .o7(net_u100_i3b) ); // ------------------------------------------------------------------------ // Read-bus output drivers: second inversion, A/B -> Ab/Bb // ------------------------------------------------------------------------ f240 u105 ( .oe1_n(aen_n), .d1_1(a0), .o2_4(ab[1]), .d1_2(a2), .o2_3(ab[3]), .d1_3(a4), .o2_2(ab[5]), .d1_4(a6), .o2_1(ab[7]), .d2_1(a7), .o1_4(ab[6]), .d2_2(a5), .o1_3(ab[4]), .d2_3(a3), .o1_2(ab[2]), .d2_4(a1), .o1_1(ab[0]), .oe2_n(aen_n) ); f240 u106 ( .oe1_n(ben_n), .d1_1(b0), .o2_4(bb[1]), .d1_2(b2), .o2_3(bb[3]), .d1_3(b4), .o2_2(bb[5]), .d1_4(b6), .o2_1(bb[7]), .d2_1(b7), .o1_4(bb[6]), .d2_2(b5), .o1_3(bb[4]), .d2_3(b3), .o1_2(bb[2]), .d2_4(b1), .o1_1(bb[0]), .oe2_n(ben_n) ); f240 u108 ( .oe1_n(aen_n), .d1_1(a8), .o2_4(ab[9]), .d1_2(a10), .o2_3(ab[11]), .d1_3(a12), .o2_2(ab[13]), .d1_4(a14), .o2_1(ab[15]), .d2_1(a15), .o1_4(ab[14]), .d2_2(a13), .o1_3(ab[12]), .d2_3(a11), .o1_2(ab[10]), .d2_4(a9), .o1_1(ab[8]), .oe2_n(aen_n) ); f240 u109 ( .oe1_n(ben_n), .d1_1(b8), .o2_4(bb[9]), .d1_2(b10), .o2_3(bb[11]), .d1_3(b12), .o2_2(bb[13]), .d1_4(b14), .o2_1(bb[15]), .d2_1(b15), .o1_4(bb[14]), .d2_2(b13), .o1_3(bb[12]), .d2_3(b11), .o1_2(bb[10]), .d2_4(b9), .o1_1(bb[8]), .oe2_n(ben_n) ); f240 u111 ( .oe1_n(aen_n), .d1_1(a16), .o2_4(ab[17]), .d1_2(a18), .o2_3(ab[19]), .d1_3(a20), .o2_2(ab[21]), .d1_4(a22), .o2_1(ab[23]), .d2_1(a23), .o1_4(ab[22]), .d2_2(a21), .o1_3(ab[20]), .d2_3(a19), .o1_2(ab[18]), .d2_4(a17), .o1_1(ab[16]), .oe2_n(aen_n) ); f240 u112 ( .oe1_n(ben_n), .d1_1(b16), .o2_4(bb[17]), .d1_2(b18), .o2_3(bb[19]), .d1_3(b20), .o2_2(bb[21]), .d1_4(b22), .o2_1(bb[23]), .d2_1(b23), .o1_4(bb[22]), .d2_2(b21), .o1_3(bb[20]), .d2_3(b19), .o1_2(bb[18]), .d2_4(b17), .o1_1(bb[16]), .oe2_n(ben_n) ); f240 u114 ( .oe1_n(aen_n), .d1_1(a24), .o2_4(ab[25]), .d1_2(a26), .o2_3(ab[27]), .d1_3(a28), .o2_2(ab[29]), .d1_4(a30), .o2_1(ab[31]), .d2_1(a31), .o1_4(ab[30]), .d2_2(a29), .o1_3(ab[28]), .d2_3(a27), .o1_2(ab[26]), .d2_4(a25), .o1_1(ab[24]), .oe2_n(aen_n) ); f240 u115 ( .oe1_n(ben_n), .d1_1(b24), .o2_4(bb[25]), .d1_2(b26), .o2_3(bb[27]), .d1_3(b28), .o2_2(bb[29]), .d1_4(b30), .o2_1(bb[31]), .d2_1(b31), .o1_4(bb[30]), .d2_2(b29), .o1_3(bb[28]), .d2_3(b27), .o1_2(bb[26]), .d2_4(b25), .o1_1(bb[24]), .oe2_n(ben_n) ); endmodule